Processor In-Field Self-Testing via Cache-Based Scan Patterns
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Solution Overview
Problem
Existing methods for scan-at-field testing in multicore processors conflict with normal operation and are cumbersome, particularly in mission-critical systems where functional safety is paramount, such as autonomous vehicles and spacecraft.
Innovation Solution
A processor configured for in-field self-testing using automated test pattern generation without external test circuitry, leveraging internal core circuitry and cache subsystems to perform probeless scan pattern testing, allowing for autonomous and optimized testing during normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-at-field testing is performed using external test circuitry and probes, then structural testing and functional safety monitoring are achieved, but normal processor operation is disrupted and testing becomes cumbersome
Solution Approach 1:
The processor performs self-testing using its own internal resources (cache memory, scan chains, control logic) without requiring external test equipment. The scan controller is integrated within the processor core, allowing autonomous execution of test patterns during field operation, thereby eliminating the need for external probes and test circuitry that would disrupt normal operation.
Solution Approach 2:
The test functionality is merged with the normal processor operation by integrating scan chains and test control logic into the existing processor architecture. The cache memory serves dual purposes: normal data storage and test pattern storage. This merging allows testing to occur without requiring separate external test equipment, reducing operational disruption.
2Manufacturing precision
If external test circuitry and probes are used for scan testing, then comprehensive structural testing is possible, but device complexity and testing cumbersome nature increase
Solution Approach 1:
The external test circuitry and probes are extracted from the system, replacing them with integrated internal test resources. The processor contains its own scan controller, scan chains, and test pattern storage within the cache memory, eliminating the need for external testing infrastructure while maintaining comprehensive structural testing capability.
Solution Approach 2:
The processor's existing components are given multiple functions: the cache memory stores both operational data and test patterns, the scan chains serve both normal data transfer and structural testing purposes, and the control logic manages both execution and testing. This multi-functionality reduces the need for additional dedicated test circuitry.
3Measurement precision
If probe-based testing is performed, then external test control is achieved, but testing time and operational downtime increase
Solution Approach 1:
Test patterns are pre-loaded into the cache memory before testing begins. The scan controller is pre-configured with test sequences and control logic. This preliminary preparation allows testing to execute quickly without requiring real-time external control, significantly reducing testing time and operational downtime.
Solution Approach 2:
The processor can transition between normal operation and self-testing modes rapidly without requiring physical reconfiguration or external probe connection/disconnection. The integrated architecture allows continuous operation with minimal interruption, as the test control logic is always present and ready to execute test patterns from cached memory.
Data Source
AI summary
In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.