Processor in Memory for Binary Convolution and Majority Voting
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Solution Overview
Problem
Conventional artificial neural networks require significant memory and computational resources for image and audio recognition tasks, limiting their miniaturization and integration capabilities due to the need for large memory to store partial sums during convolutional operations.
Innovation Solution
A processor in memory that combines a time domain signal processor and content addressable memory to perform binary convolution and majority voting operations, reducing the need for additional memory by directly calculating input feature maps and filters through XNOR operations and binarization, allowing for simultaneous evaluation of multiple match lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional artificial neural networks are used for image and audio recognition, then recognition accuracy is improved, but memory requirements and computational resources increase significantly
Solution Approach 1:
The patent applies parameter changes by transforming the data representation from conventional multi-bit values to binary values (0 or 1). This binarization of weights and input data reduces the memory requirements from storing multi-bit values to storing single-bit values, achieving significant compression while maintaining recognition accuracy through the mathematical equivalence of binary neural network operations to conventional operations.
Solution Approach 2:
The patent uses copying by storing binary weight values in memory cells that can be rapidly accessed and replicated during inference operations. The content-addressable memory architecture allows for efficient copying of binary weight patterns to multiple match lines simultaneously, enabling parallel computation without requiring large amounts of additional memory storage.
2Reliability
If conventional artificial neural networks are used for image and audio recognition, then recognition accuracy is improved, but device size and integration capability deteriorate
Solution Approach 1:
By changing the data parameter from multi-bit to single-bit binary representation, the patent reduces the area required for memory storage by a factor equal to the bit reduction. This allows the same recognition accuracy to be achieved in a much smaller device footprint, improving integration capability for mobile and embedded applications.
Solution Approach 2:
The patent merges the weight storage function with the computation function by using the same memory cells for both purposes. The content-addressable memory structure allows weights to be stored and simultaneously used for parallel comparison operations, eliminating the need for separate storage and computation units that would increase device size.
3Speed
If binary convolution and majority voting operations are performed using content addressable memory, then operation speed is improved, but computational complexity increases
Solution Approach 1:
The patent replaces the mechanical computation system with an electrical memory-based system. Instead of performing sequential multiplication and addition operations, the system uses electrical memory cells to perform parallel binary comparisons through voltage level interactions. This substitution of computation mechanism with memory interaction dramatically speeds up operations while the binary nature simplifies the computational logic.
Solution Approach 2:
The content-addressable memory structure provides self-service by automatically performing the comparison and matching operations without external computational intervention. When input data is applied to the match lines, the memory cells automatically compare against stored binary weights and generate output signals based on the majority voting rule, eliminating the need for complex external computation circuits.
Data Source
AI summary
Disclosed are an artificial neural network device and a method of operating the same. The artificial neural network device includes an operation part performing an artificial neural network operation on an input feature map and a classification part performing a classifying operation on the input feature map based on the artificial neural network operation of the operation part. The operation part includes an XNOR operation circuit performing an XNOR operation on the input feature map and a filter and a binarizing circuit performing a binarization operation based on the result of the XNOR operation of the XNOR operation circuit. Accordingly, the artificial neural network device is miniaturized and performs the operation at high speed.