Processor Instruction Cache Dual-Read Modes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current processor memory access techniques consume significant energy due to the need to individually access and latch each instruction cell, leading to wasteful re-toggling of row paths and precharging of bit lines for multiple read cycles, resulting in inefficient power usage.
Innovation Solution
A multi-mode accessing control module that enables a processor to operate in both discrete and sequential read modes, where a single word line pulse is used to access multiple cells, reducing the need for repeated row path toggling and bit line precharging, and extending the word line signal period to enhance bit line separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual cell access with repeated word line toggling is used, then each instruction cell can be accessed accurately, but energy consumption increases due to repeated row path toggling and bit line precharging
Solution Approach 1:
The patent applies preliminary action by precharging bit lines only once before a sequence of reads and maintaining word line assertion across multiple read cycles. This eliminates the need to repeatedly toggle word lines and precharge bit lines for each individual read operation, thereby reducing energy consumption while maintaining accurate cell access throughout the sequence.
Solution Approach 2:
The patent implements continuity of useful action by keeping the word line asserted continuously across multiple read cycles rather than toggling it off and on for each read. This continuous assertion allows the memory array to remain in an active state, enabling sequential reads without the energy penalty of repeated row path toggling and bit line precharging.
2Ease of operation
If word line is toggled for each read cycle, then individual cell access is enabled, but processing efficiency decreases due to repeated access cycles
Solution Approach 1:
The control module performs preliminary actions by precharging bit lines once and asserting the word line before a sequence of reads. This setup enables multiple individual cell accesses to occur during the continuous word line assertion period, eliminating the need for repeated toggling and improving processing efficiency while maintaining individual cell access capability.
Solution Approach 2:
The patent transforms the periodic toggling of word lines into a continuous assertion pattern. Instead of periodically enabling and disabling the word line for each read cycle, the word line remains asserted continuously, allowing multiple reads to occur within a single assertion period. This reduces the frequency of toggling operations and improves overall processing efficiency.
3Measurement precision
If bit lines are precharged for each read cycle, then accurate sensing is achieved, but power usage increases due to repeated precharging
Solution Approach 1:
The control module performs preliminary precharging of bit lines once before a sequence of reads during continuous word line assertion. This single precharging action suffices for multiple read operations, eliminating the need to repeatedly precharge bit lines for each read cycle. Sensing accuracy is maintained because bit lines are properly precharged before the read sequence begins, while power consumption is reduced by eliminating redundant precharging operations.
Data Source
AI summary
A processor including a memory and a control module. The memory has an array of cells. The control module is configured to: determine a number of access cycles along a first word line; determine an extended period based on the number of the access cycles; generate a word line signal to maintain the first word line in an activated state during (i) an initial period and (ii) the extended period; and access a first cell during the extended period. The first cell is connected to the first word line. The control module is further configured to deactivate the word line and maintain the first word line in a deactivated state while accessing a second cell connected to the first word line. The accessing of the second cell is based on a bit line separation provided during the extended period.