Processor Function Unit Instruction Collision Avoidance
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Solution Overview
Problem
Superscalar processors face inefficiencies due to instruction collisions, where multiple function units attempting to execute the same instruction lead to wasted computational resources and potential data errors, prompting the execution of 'no operation' instructions to avoid collisions.
Innovation Solution
Implementing a processor with dual instruction-selection logic circuits that use different selection techniques for each function unit, ensuring that if both units select the same instruction, the second unit employs an alternative technique to execute a different instruction, thereby preventing collisions and NOP execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple function units use the same instruction selection technique, then the selection process is simple and consistent, but instruction collisions occur frequently causing wasted computational resources
Solution Approach 1:
Different function units are assigned different instruction selection techniques based on their specific characteristics and the types of instructions they execute. This local differentiation reduces collisions while maintaining overall system consistency.
Solution Approach 2:
The selection criteria parameters are changed between different function units - while the first function unit uses one selection technique, the second function unit uses a different technique, transforming the selection behavior to avoid collisions.
2Quantity of substance
If multiple function units simultaneously execute the same instruction, then resource utilization appears high, but data errors occur and computational time is wasted
Solution Approach 1:
The system proactively prevents instruction collisions before they can cause data errors by using different selection techniques. This preliminary preventive action ensures reliable execution while maintaining high instruction throughput.
Data Source
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AI summary
An embodiment of a technique for selecting instructions for execution from an issue queue at multiple function units while reducing the chances of instruction collisions. Each function unit in a processor may include a selection logic circuit that selects a specific instruction from the issue queue for execution. In order to avoid instruction collision, a function unit may have a selection logic circuit that may select two instructions from an instruction queue: one according to a first selection technique and one according to a second selection technique. Then, by comparing the instruction selected by the first selection technique to the instruction selected by the selection logic circuit of another function unit, the instruction selected by the second technique may be used instead if there will be an instruction collision because the instruction selected by the first selection technique is the same as the instruction selected at a different function unit.