Processor Instruction Compression via Bit Relationship Identification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Custom processors require significant memory resources to store instruction sequences due to the need for long instruction words, which can be inefficiently used in applications with predictable functionality.
Innovation Solution
The method involves identifying relationships between bit positions in instruction sequences to generate a compressed form, using a decoder with logic circuitry to convert compressed bits into uncompressed instructions, reducing memory requirements while allowing efficient decompression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If instruction sequences are stored in uncompressed format, then the processor can execute instructions correctly, but significant memory resources are occupied
Solution Approach 1:
The patent uses template copying where common instruction patterns are stored as templates and replicated through substitution. Instead of storing full uncompressed instructions repeatedly, the system stores a template once and generates multiple copies by substituting specific parameters, significantly reducing memory usage while maintaining execution correctness
Solution Approach 2:
The patent changes the representation parameters of instructions by using compressed encoding schemes. Instructions are encoded with variable-length fields and parameter substitutions that reduce the average number of bits required to represent each instruction, thereby reducing memory resources while preserving the ability to correctly execute instructions
2Quantity of substance
If compression is applied to instruction sequences, then memory resources are reduced, but decompression complexity increases
Solution Approach 1:
The patent segments the decompression process into distinct stages: template matching, parameter extraction, and instruction reconstruction. The decoder is divided into multiple functional units that handle different aspects of decompression, making the overall complex process manageable and implementable with systematic logic circuitry
Solution Approach 2:
The patent performs preliminary organization of compressed instruction data during the coding phase, structuring it in a way that facilitates efficient decoding. The compressed representation is designed with predetermined patterns and structures that allow the decoder to anticipate and prepare for specific decoding operations, reducing the complexity of real-time decompression
3Quantity of substance
If entropy coding is used based on instruction probabilities, then average code length is reduced, but coding complexity increases
Solution Approach 1:
The patent changes the approach from probability-based entropy coding to pattern-based template matching. Instead of requiring complex probability calculations and variable-length encoding tables, the system uses fixed patterns and parameter substitutions that achieve compression with simpler, more deterministic coding logic
Solution Approach 2:
The patent discards redundant information in favor of essential parameters during compression, then recovers the full instruction information during decompression through template substitution. This approach achieves compression by eliminating repetitive patterns while preserving the ability to reconstruct complete instructions, balancing code length reduction with coding simplicity
Data Source
AI summary
A custom processor is adapted for performing at least one predetermined application. The instruction sequence for the custom processor is compressed by performing at least one identification process on the instructions of the instruction sequence, in order to identify relationships between the contents of the bit positions in the instructions. A compressed instruction sequence then includes one compressed instruction corresponding to each instruction of the predetermined instruction sequence, with each compressed instruction comprising a reduced number of bits, based on the identified relationships between the contents of said bit positions in said instructions of said predetermined instruction sequence.