Pipelined Processor Without Instruction Counter
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Solution Overview
Problem
Conventional pipelined processors require substantial integrated circuit area due to the presence of an instruction counter and associated control circuitry, limiting their compactness and efficiency.
Innovation Solution
A pipelined run-to-completion processor design that omits the instruction counter, initiating instruction fetching only through external input data or initial fetch information, allowing for a compact implementation in approximately ten thousand equivalent gates, and featuring a lookup table circuit to determine memory addresses and a pop stack absolute instruction for conditional operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an instruction counter and associated control circuitry are included in a pipelined processor, then the processor can automatically track and fetch instructions sequentially, but the integrated circuit area increases substantially
Solution Approach 1:
The patent removes the instruction counter and its associated control circuitry from the processor architecture. Instead of automatic sequential tracking, the processor relies on external entities (host processor or DMA controller) to provide fetch information, thereby eliminating the circuitry that would otherwise occupy substantial integrated circuit area.
Solution Approach 2:
The patent introduces an intermediary mechanism where external entities (host processor or DMA controller) act as mediators to supply fetch information to the processor. This external control approach replaces the internal instruction counter, allowing the processor to fetch instructions without requiring substantial on-chip control circuitry.
2Productivity
If a lookup table circuit is used to convert table number to base address, then memory address determination becomes efficient, but the processor complexity increases
Solution Approach 1:
The patent pre-organizes memory into tables with predetermined base addresses and stores mapping information in lookup tables. When fetch information is received, the base address is quickly retrieved from the lookup table without requiring complex real-time calculation, thus improving efficiency while keeping the added complexity minimal and localized.
3Loss of energy
If the processor is designed to run to completion without instruction counter, then power consumption is reduced, but the processor requires external prompting to start and resume operation
Solution Approach 1:
The patent employs periodic action where the processor operates in sleep mode between execution tasks and is periodically activated by external fetch information. This allows the processor to consume minimal power during idle periods while still being able to start and resume execution when prompted by external entities with new input data or fetch information.
Data Source
AI summary
A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.