Processor Instruction Criticality Scheduling
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Solution Overview
Problem
Existing processors lack an efficient method to optimize program running efficiency by determining the importance of instructions in the execution process, leading to suboptimal operation sequences and resource allocation.
Innovation Solution
The proposed solution involves obtaining criticality information for instructions based on factors like dependency relationships, pipeline execution, and hit information, which is used to determine and update the operation sequence, including fetch, decode, execute, and prefetch operations, thereby enhancing the program's running efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are executed in traditional pipelined order, then the processor can maintain steady execution flow, but program running efficiency cannot be optimized because all instructions are treated equally without considering their importance
Solution Approach 1:
The patent assigns different criticality values to different instructions based on their importance to program execution. The instruction cache stores both instructions and their associated criticality information, enabling the processor to identify and prioritize critical instructions locally without redesigning the entire execution pipeline. This localized differentiation resolves the contradiction by optimizing efficiency through selective instruction treatment rather than universal processing changes.
Solution Approach 2:
The criticality information for each instruction is determined and stored in the instruction cache before the instruction is executed. This preliminary assignment of priority levels allows the execution unit to pre-identify which instructions require accelerated processing, enabling efficient scheduling decisions to be made in advance rather than during execution, thus improving overall program running efficiency without adding runtime complexity.
2Speed
If the processor executes instructions out of order to improve efficiency, then execution speed increases, but wait times and pipeline stalls may increase due to improper sequencing of critical instructions
Solution Approach 1:
The patent implements a feedback mechanism where the execution unit monitors pipeline status and criticality information, then adjusts the execution order dynamically. When a pipeline stall is detected or anticipated, the system uses the stored criticality values to reorder instructions, prioritizing critical ones to minimize stall time. This feedback-driven reordering resolves the contradiction by maintaining high execution speed while actively managing and reducing pipeline stall losses.
3Productivity
If all instructions are processed with equal priority, then the instruction pipeline operates smoothly, but resource allocation is suboptimal and cannot be optimized for important instructions
Solution Approach 1:
The patent introduces a new parameter - criticality value - that characterizes each instruction's importance. By storing this parameter in the instruction cache alongside instructions, the system enables differentiated resource allocation based on instruction priority. Critical instructions receive preferential treatment in terms of execution timing and resource allocation, while non-critical instructions follow standard processing. This parameter-based differentiation resolves the contradiction by optimizing resource allocation efficiency without significantly complicating the instruction processing mechanism.
Data Source
AI summary
Disclosed in embodiments of the present disclosure are a processor and an instruction operation method. The method includes obtaining criticality information of an instruction, wherein the criticality information of the instruction indicates importance degree of the instructions in a running process of a program; determining an operation sequence of the instruction based on the criticality information; and performing operations for the instruction based on the determined operation sequence of the instruction.