Processor Instruction Decode Part Dynamic Opcode Switching
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Solution Overview
Problem
Conventional semiconductor processing devices with added application-specific instructions face limitations in defining the number of executable general and additional instructions due to the limited number of instruction regions, leading to increased circuit complexity when trying to extend the instruction code map.
Innovation Solution
A processor with an arithmetic unit, instruction decode part, and interrupt register that switches opcode sets based on interrupt signals, allowing for additional instructions to be executed efficiently without increasing the circuit scale by utilizing a multi-interrupt structure and dynamic opcode switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the instruction code map is extended to increase the number of executable instructions, then the number of executable general and additional instructions is improved, but the circuit scale is increased considerably
Solution Approach 1:
The patent implements dynamic switching of instruction code maps based on interrupt signals. The instruction decode part selectively activates different code maps (first code map for general instructions, second code map for additional instructions) depending on the interrupt type, allowing the system to adapt the instruction set dynamically without requiring a permanently large static code map structure.
Solution Approach 2:
The instruction code map is divided into multiple segmented code maps: a first instruction code map for general instructions and a second instruction code map for additional instructions. Each code map is independently stored and can be selectively activated, allowing the system to load only the necessary instruction set based on the current operation context, thereby reducing the overall circuit scale requirement.
2Productivity
If dedicated interfaces and dedicated opcodes are allocated for additional instructions, then the processing capability for additional instructions is improved, but the numbers of executable general instructions and additional instructions are limited
Solution Approach 1:
The patent creates a universal instruction decode part that can handle both general instructions and additional instructions through a single unified structure. The decode part uses interrupt signals to determine which code map to activate, allowing one decode unit to serve multiple instruction types without requiring separate dedicated interfaces for each instruction category.
Solution Approach 2:
The patent introduces a new dimension of instruction selection by using interrupt signals as a control mechanism. Instead of having separate dedicated interfaces for different instruction types, the system uses the interrupt signal dimension to select between different code maps, thereby expanding the number of executable instructions without adding proportional hardware complexity.
Data Source
AI summary
A processor includes: an arithmetic unit configured to execute instructions; an instruction decode part configured to decode the instructions executed in the arithmetic unit and to output opcodes; and an interrupt register configured to receive interrupt signals, wherein the instruction decode part includes an instruction code map that stores the opcodes in correspondence to instructions and outputs the opcodes in accordance with the instructions inputted, and the instruction code map stores a plurality of sets of opcodes to be output as switch opcodes corresponding to additional instructions, the additional instructions are a part of the instructions, and switches the sets of the switch opcodes in accordance with the interrupt signal.