Processor Instruction Dispatch Circuit Reducing Latency
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Solution Overview
Problem
Prior processor architectures face inefficiencies due to redundant instruction and data circuitry, misaligned timing between instruction and data buses, large storage overhead, and high bandwidth requirements, leading to decreased processing efficiency.
Innovation Solution
A processor configuration with a computational array and an instruction dispatch circuit that processes raw instructions through an instruction dispatch unit (IDU) to generate processed instructions, which are dispatched to computational elements via instruction queues, allowing for efficient instruction dispatch by shifting instructions in multiple directions and optimizing data and instruction timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional instruction dispatch mechanisms are used, then instruction processing can be performed, but processing efficiency decreases due to redundant circuitry and misaligned timing
Solution Approach 1:
The patent combines instruction storage and data storage into a unified memory structure, eliminating separate instruction cache and data cache. Instructions and data are stored together in the same memory array, accessed through a single unified interface, which removes redundant circuitry while maintaining efficient access to both instructions and data simultaneously
Solution Approach 2:
The unified memory structure serves multiple functions: it stores both instructions and data, provides simultaneous access to both through the same interface, and eliminates the need for separate instruction and data pathways. This multi-functional approach reduces overall system complexity while improving processing efficiency
2Productivity
If separate instruction cache and data cache are used, then instruction and data access can be performed independently, but large storage overhead is required
Solution Approach 1:
The patent merges separate instruction cache and data cache into a single unified memory structure, reducing total storage overhead. By storing instructions and data together in the same memory array with a single unified interface, the system eliminates duplicate storage resources while maintaining independent access capabilities through the unified memory interface
3Productivity
If traditional instruction dispatch is used, then instructions can be executed, but high channel bandwidth is required to transfer instructions from main memory
Solution Approach 1:
The unified memory structure pre-loads and stages both instructions and data simultaneously in a single memory array before execution. This preliminary organization allows the instruction dispatch unit to access ready-available instructions without requiring high-bandwidth continuous transfers from main memory, reducing the energy and bandwidth requirements for instruction transfer
Data Source
AI summary
A processor comprises a computational array of computational elements and an instruction dispatch circuit. The computational elements receive data operands via data lanes extending along a first dimension, and processes the operands based upon instructions received from the instruction dispatch circuit via instruction lanes extending along a second dimension. The instruction dispatch circuit receives raw instructions, and comprises an instruction dispatch unit (IDU) processor that processes a set of raw instructions to generate processed instructions for dispatch to the computational elements, where the number of processed instructions is not equal to the number of instructions of the set of raw instructions. The processed instructions are dispatched to columns of the computational array via a plurality of instruction queues, wherein an instruction vector of instructions is shifted between adjacent instruction queues in a first direction, and dispatches instructions to the computational elements in a second direction.