Processor Instruction Execution Mode Control for Atomic Sequences
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Solution Overview
Problem
Processor systems face challenges in achieving user-control over the precise semantics of instruction execution due to asynchronous events like interrupts, which disrupt normal program flow and make timing and tracing inaccurate, and can induce failures in state-switching scenarios.
Innovation Solution
A processor is controlled according to an execution mode specified for an instruction sequence, where information from the instruction stream is supplied to execution units, recognizing the start of a sequence and controlling operations to ensure atomic execution by disabling interrupts and managing asynchronous events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If interrupts and asynchronous events are enabled in the processor system, then the system responds to external events and maintains flexibility, but the timing and tracing of instruction execution become inaccurate and program flow is disrupted
Solution Approach 1:
The processor divides instruction execution into atomic sequences that are isolated from interrupt interference. By segmenting the execution flow into protected atomic units, the system maintains responsiveness to external events while ensuring accurate timing and tracing within each atomic sequence.
Solution Approach 2:
The invention introduces execution mode as an intermediary layer between the instruction stream and the execution units. This intermediary controls whether interrupts are enabled or disabled during specific instruction sequences, allowing the system to balance responsiveness with timing accuracy based on the current execution context.
2Measurement precision
If interrupts are disabled to achieve atomic execution sequences, then timing and tracing accuracy is improved, but the system loses responsiveness to external events
Solution Approach 1:
The processor dynamically adjusts interrupt enablement based on the execution mode of the current instruction sequence. Rather than maintaining a static interrupt state, the system transitions between enabled and disabled states according to whether the current sequence requires atomic execution, optimizing both timing accuracy and system responsiveness.
Solution Approach 2:
The invention applies different interrupt handling policies to different portions of the instruction stream. Atomic sequences have interrupts disabled locally to ensure timing accuracy, while non-atomic sequences allow interrupts to maintain system responsiveness, creating localized quality variations in interrupt handling.
3Adaptability or versatility
If the processor executes instructions with flexible interrupt handling, then system versatility is maintained, but user-control over precise execution semantics is lost
Solution Approach 1:
The invention changes the execution mode parameter to control interrupt behavior during instruction sequence execution. By modifying this parameter based on the sequence type (atomic vs. non-atomic), the system maintains versatility while giving users precise control over execution semantics through the execution mode mechanism.
Data Source
AI summary
In a processor, instructions of an instruction stream are supplied to an execution unit which executes the supplied instructions according to respective execution modes. A control unit recognizes a user-defined instruction sequence (UDIS) in the instruction stream. The UDIS is associated with a UDIS definition provided in-line and/or as contents of machine-state registers (MSRs), and specifying, at least in part, a start, optionally an end, and a particular execution mode for the UDIS. Subsequently, ones of the instructions of the UDIS are executed in accordance with the particular execution mode, such as by optionally altering recognition of asynchronous events. For example, disabling hardware interrupts during the executing results in apparent atomic execution. Fetching, decoding, issuing, and/or caching of the instructions of the UDIS are optionally dependent on the particular execution mode. MSRs optionally specify a maximum length and/or execution time.