Processor Instruction Execution Synchronization via Iterative Geometric Progression

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Solution Overview

Problem

In safety-critical and mission-critical applications, synchronizing multiple processors to ensure reliable and consistent instruction execution is challenging, as discrepancies in operation timing can lead to unreliable results.

Innovation Solution

A method and system where processors iteratively execute instructions in a geometric progression, reducing the number of instructions in each iteration, and determining the total number executed within a predetermined time period, ensuring synchronization and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If processors execute instructions in a synchronous manner to ensure reliable results, then reliability is improved, but device complexity increases due to the need for precise timing control and coordination mechanisms

Engineering Contradiction:
Improvereliability of resultsVSAvoidcomplexity of synchronization control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the instruction execution process into multiple iterations, where each iteration executes a controlled number of instructions. This segmentation allows the system to maintain synchronization across processors while breaking down the complex timing control into manageable discrete steps, thereby improving reliability without proportionally increasing overall system complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic action by having processors execute instructions in repeated iterations with predetermined time periods. Each iteration follows a structured pattern of executing a specific number of instructions, then checking timing constraints. This periodic structure enables reliable synchronous operation while using simple, repeating control logic rather than complex continuous coordination mechanisms

Inventive Principle:
Principle #19Periodic action

2Reliability

If processors execute a fixed number of instructions within a specific time period to maintain synchronization, then reliability is improved, but productivity decreases due to the constraints on instruction execution flexibility

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidinstruction execution throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies dynamics by making the number of instructions executed in each iteration dependent on the iteration number, following a geometric progression pattern. This dynamic adjustment allows the system to maintain synchronization constraints while optimizing instruction throughput - executing more instructions in early iterations when time is abundant, and fewer instructions in later iterations as the time period progresses, thereby balancing reliability and productivity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of instruction count dynamically based on the iteration number and time remaining in the predetermined period. By adjusting this parameter according to a geometric progression formula, the system maintains synchronization accuracy while maximizing overall instruction execution productivity within the time constraints

Inventive Principle:
Principle #35Parameter changes

3Reliability

If processors monitor and control the number of instructions executed in each iteration to ensure synchronization, then reliability is improved, but device complexity increases due to additional monitoring and control mechanisms

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidcomplexity of monitoring mechanisms
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback by having each processor monitor its own instruction execution count and compare it against the expected count for the current iteration. This self-feedback mechanism ensures synchronization reliability without requiring complex inter-processor monitoring infrastructure, as each processor independently verifies its own execution progress against the predetermined geometric progression schedule

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9256426B2Controlling total number of instructions executed to a desired number after iterations of monitoring for successively less number of instructions until a predetermined time period elapse
Publication Date: 2016.02.09 GENERAL ELECTRIC CO
  • US9256426B2 patent drawing
  • US9256426B2 patent drawing
  • US9256426B2 patent drawing

AI summary

A system and method for controlling processor instruction execution. In one example, a method for controlling a total number of instructions executed by a processor includes instructing the processor to iteratively execute instructions via multiple iterations until a predetermined time period has elapsed. A number of instructions executed in each iteration of the iterations is less than a number of instructions executed in a prior iteration of the iterations. The method also includes determining the total number of instructions executed during the predetermined time period.