Processor Instruction Issuance Control for Hazard Detection
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Solution Overview
Problem
Conventional control mechanisms for judging data dependency of instructions cannot be applied to processors with reduced functional units or altered architectures, leading to issues with simultaneous execution of instructions, especially when circuit area is saved or single-cycle instructions are converted to multi-cycle instructions.
Innovation Solution
A processor design that includes an instruction buffer, an instruction decoding unit, and an instruction issuance control unit which detects factors obstructing simultaneous execution, allowing sequential supply of instructions when necessary, without modifying object codes or changing instruction buffer storage methods, and judges execution possibility using static instruction information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of functional units is reduced to save circuit area, then circuit area is reduced, but the ability to execute instructions simultaneously is degraded
Solution Approach 1:
The instruction issuance control unit performs preliminary analysis of instruction groups to detect factors obstructing simultaneous execution before instructions are sent to the execution stage. By identifying hazards in advance and controlling instruction supply accordingly, the system enables efficient utilization of reduced functional units without compromising correctness.
Solution Approach 2:
The instruction issuance control unit acts as an intermediary between the instruction buffer and the execution stage. It analyzes instruction groups, detects hazards, and controls the timing of instruction issuance to the decoding unit, thereby coordinating the operation of reduced functional units to avoid conflicts.
2Area of stationary object
If single-cycle instructions are changed into multi-cycle instructions, then circuit area is reduced, but the complexity of execution control increases
Solution Approach 1:
The system performs preliminary detection of multi-cycle instructions and factors obstructing simultaneous execution in the instruction group before execution. This advance identification allows the control unit to manage the execution timing and coordination of multi-cycle instructions systematically, reducing the perceived complexity during actual execution.
3Reliability
If conventional hazard detection is used during execution stage, then data dependency hazards are detected, but the method cannot be applied to processors with altered architecture or reduced functional units
Solution Approach 1:
Instead of detecting hazards during the execution stage, the invention performs hazard detection in advance at the instruction issuance stage. The instruction issuance control unit analyzes the instruction group to detect factors obstructing simultaneous execution before instructions are sent to the execution stage, making the hazard detection mechanism architecture-independent and adaptable to various processor configurations.
Solution Approach 2:
The instruction issuance control unit serves as an intermediary that implements a universal hazard detection mechanism. It analyzes instruction groups using static information and controls instruction supply accordingly, providing architecture-adaptive hazard detection that works across different processor configurations without requiring modification to the execution stage.
4Area of stationary object
If the number of counters is reduced to save circuit area, then circuit area is reduced, but the ability to manage multi-cycle instructions simultaneously is degraded
Solution Approach 1:
The instruction issuance control unit acts as an intermediary that manages the coordination of multiple multi-cycle instructions using a reduced number of counters. It analyzes the instruction group to identify multi-cycle instructions and their execution requirements, then controls their issuance timing to ensure proper management despite having fewer counters available.
Data Source
AI summary
A processor includes: an instruction buffer which holds a group of instructions that can be executed in parallel; an instruction decoding unit which decodes part or all of the group of instructions; and an instruction issuance control unit which detects whether or not a factor obstructing simultaneous execution of the group of instructions exists in the group of instructions and supplies the group of instructions to the instruction decoding unit by controlling the instruction buffer so that the instructions of the group of instructions are sequentially supplied when the factor exists and all the instructions of the group of instructions are simultaneously supplied when the factor does not exist.