Processor Instruction Set Extension via Dynamic Microcode
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Solution Overview
Problem
Existing technologies face inefficiencies and high costs due to poor portability and performance when executing bytecode or intermediate representations on processors with different Instruction Set Architectures (ISAs), particularly due to 1:N mapping issues and the need for costly extensions like Jazelle for ARM-based processors.
Innovation Solution
A dynamic approach that identifies unsupported instructions by processing circuitry, extends the processor's instruction set through microcode updates, and executes computer programs by adding necessary microinstructions or macroinstructions, allowing for efficient execution on arbitrary processors without requiring extensive software support or emulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If static code generation is used for mapping intermediate representation operations to native architecture instructions, then code generation is simplified, but portability deteriorates and performance is reduced
Solution Approach 1:
The patent implements dynamic code generation where the runtime system adapts the mapping between intermediate representation operations and native architecture instructions based on the target processor's specific instruction set architecture. This allows the same bytecode to be efficiently executed on different ISAs (x86, ARM, RISC-V) by dynamically generating architecture-specific code rather than using static mappings, thereby improving portability while maintaining generation simplicity through automated runtime adaptation.
2Adaptability or versatility
If extensive software support and emulation are used to support multiple ISAs, then compatibility is improved, but device complexity and costs increase
Solution Approach 1:
The patent introduces a runtime system as an intermediary layer between the intermediate representation and the native architecture. This runtime dynamically translates and maps operations from the intermediate representation to the target ISA's native instructions, eliminating the need for extensive pre-written software support for each ISA combination. The runtime acts as a mediator that handles the complexity of ISA translation automatically, reducing overall system complexity while maintaining broad compatibility.
Solution Approach 2:
The runtime system provides universal support for multiple ISAs through a single unified implementation. Instead of requiring separate software support packages for each ISA combination, the runtime uses a universal approach to dynamically adapt to different target architectures, enabling one runtime to handle x86, ARM, RISC-V, and other ISAs efficiently, thereby reducing device complexity and costs.
3Speed
If JIT compilation is used to generate code for execution, then execution speed is improved, but energy efficiency deteriorates due to higher computational overhead
Solution Approach 1:
The patent optimizes the JIT compilation process by dynamically adjusting compilation parameters and code generation strategies based on the target ISA and execution context. The runtime system changes compilation parameters such as optimization level, code generation mode, and instruction selection to match the specific processor architecture, thereby achieving fast execution while minimizing the computational overhead and energy consumption associated with JIT compilation.
Data Source
AI summary
Various examples relate to an apparatus, device, method, and computer program for extending instructions supported by a processor. The apparatus is configured to identify at least a part of a computer program targeting an instruction unsupported by a pre-defined set of instructions of an Instruction Set Architecture (ISA) of the processor. The apparatus is configured to extend the instructions supported by the processor, based on the targeted unsupported instruction. The apparatus is configured to execute the computer program.