Processor Instruction Synchronization via Dynamic Iteration Control
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Solution Overview
Problem
In safety-critical and mission-critical applications, synchronizing the execution of instructions across multiple processors is challenging, leading to unreliable results if processors do not begin and end operations at substantially the same time.
Innovation Solution
A system and method for synchronizing processor instruction execution, utilizing a high-integrity system design with multiple synchronized processors, replicated state machines, and a distributed consensus algorithm to ensure real-time synchronization and reliable output, without requiring specialized hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors operate asynchronously to improve processing speed and productivity, then execution synchronization becomes difficult to maintain, leading to unreliable results
Solution Approach 1:
The patent implements a feedback mechanism where processors continuously monitor and report their execution state to a synchronization controller. The controller adjusts instruction issuance dynamically based on feedback from all processors to maintain synchronized execution boundaries, resolving the contradiction between asynchronous processing speed and synchronization reliability.
Solution Approach 2:
The system dynamically adapts processor execution rates and instruction batching based on real-time performance metrics and synchronization requirements. This dynamic adjustment allows processors to operate at optimal speeds while maintaining the necessary synchronization for reliable results in safety-critical applications.
2Reliability
If processors are synchronized to ensure reliable results, then processing flexibility and adaptability are reduced
Solution Approach 1:
The patent segments processing into distinct synchronized blocks or batches of instructions that can be executed in parallel across multiple processors. Each segment maintains synchronization boundaries while allowing independent optimization within segments, preserving both reliability and adaptability for different workloads.
Solution Approach 2:
The synchronization mechanism is designed to be universally applicable across different processor architectures and instruction types. The system can synchronize various kinds of operations (arithmetic, logical, memory access) using a unified approach, maintaining reliability while adapting to diverse processing requirements.
3Reliability
If specialized hardware is used to achieve processor synchronization, then system reliability improves but device complexity increases
Solution Approach 1:
The patent introduces a software-based synchronization controller that acts as an intermediary between processors and the instruction stream. This mediator manages synchronization logic, instruction batching, and processor coordination without requiring specialized hardware circuits, reducing device complexity while maintaining synchronization reliability.
Solution Approach 2:
The system replaces hardware-based synchronization mechanisms with software-controlled instruction issuance and processor coordination. By substituting mechanical/hardware synchronization circuits with software logic, the patent reduces hardware complexity while achieving the same synchronization reliability through programmable control.
Data Source
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AI summary
A system (26) and method for controlling processor (34,36,38,44,46,48) instruction execution. In one example, a method for synchronizing a number of instructions performed by processors includes instructing a first processor to start executing blocks of instructions via a first set of iterations until a predetermined time period has elapsed. A number of instructions executed in each iteration of the first set of iterations is less than a number of instructions executed in a prior iteration of the first set of iterations. The method also includes instructing a second processor to start executing blocks of instructions via a second set of iterations until the predetermined time period has elapsed. A number of instructions executed in each iteration of the second set of iterations is less than a number of instructions executed in a prior iteration of the second set of iterations. The method includes executing additional instructions by one of the processors if the numbers of instructions executed by the first and the second processor differ.