Processor Instruction Synchronization for Variable Memory Latency
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Solution Overview
Problem
Existing processors face challenges in synchronizing data movement instructions with arithmetic instructions when dealing with memory access latencies that are inconsistent, leading to decreased processing performance.
Innovation Solution
A processor design that includes an arithmetic circuit and a register to hold data, with a data movement synchronization mechanism that uses tags to ensure data movement completion before executing arithmetic instructions, thereby synchronizing data movement and operation execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is read from memory with inconstant access latency to execute an operation, then processing flexibility is improved, but synchronization between data movement and operation execution becomes difficult
Solution Approach 1:
The system performs preliminary actions by issuing the data movement instruction and arithmetic instruction in parallel before the data movement is complete. The arithmetic instruction is held in a buffered state and automatically executed once the data movement completes, eliminating the need for polling or waiting instructions that would reduce processing flexibility.
Solution Approach 2:
The synchronization mechanism uses feedback from the data movement completion status to trigger the arithmetic instruction execution. When the data movement instruction completes transferring data from memory to the register, this completion signal feeds back to automatically release and execute the corresponding arithmetic instruction, ensuring reliable synchronization without manual intervention.
2Reliability
If synchronization is achieved by inserting detection instructions executed by the core, then synchronization reliability is improved, but processing performance decreases
Solution Approach 1:
The synchronization detection function is extracted from the core execution path and implemented as a separate hardware mechanism. Instead of requiring the core to execute detection instructions, the system uses dedicated synchronization circuitry that monitors data movement completion and automatically triggers the corresponding arithmetic instruction, removing unnecessary instructions from the core's workload.
Solution Approach 2:
The arithmetic instruction automatically executes itself once the data movement completes, without requiring external detection or triggering by the core. The instruction enters a buffered state and self-activates when its data dependency is satisfied, eliminating the need for polling loops or detection instructions that would consume core cycles.
3Adaptability or versatility
If the number of cycles from data movement instruction to arithmetic instruction varies, then adaptability to different memory access patterns is improved, but compiler ability to generate synchronized instruction sequences deteriorates
Solution Approach 1:
The compiler can generate instruction sequences with parallel data movement and arithmetic instructions without needing to calculate or predict memory access latencies. The data movement instruction and arithmetic instruction are issued together in advance, and the hardware automatically handles the timing synchronization, simplifying the compiler's task while maintaining adaptability to varying memory access patterns.
Data Source
AI summary
A processor includes an arithmetic circuit configured to execute an arithmetic instruction; and a register configured to hold data used by the arithmetic circuit. The processor receives a data movement instruction and the arithmetic instruction corresponding to the data movement instruction, and moves the data from a first memory to the register based on a data movement instruction. The arithmetic circuit executes the arithmetic instruction after a data movement of the data movement instruction is completed.