Processor Instruction Translation for Legacy Microarchitecture Compatibility
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Solution Overview
Problem
Existing processors face significant challenges in implementing new instructions from subsequent generations without modifying their microarchitecture, requiring extensive design and testing efforts and incurring high costs.
Innovation Solution
A method and processor system that determines whether an instruction is a target instruction, executing it in a first mode if not, and simulating its execution using basic decoding information stored in an internal register when it is a target instruction, allowing new instructions to be supported without altering the microarchitecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If new instructions are implemented on previous generation processors by modifying microarchitecture, then instruction compatibility is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent uses a translation mechanism that copies the functionality of new instructions into a form that the old processor can understand. A translation layer intercepts new instructions and translates them into equivalent sequences of old instructions, allowing the processor to execute new instruction sets without physically modifying its microarchitecture. This copying approach enables instruction compatibility while preserving the original device complexity.
Solution Approach 2:
The patent introduces a translation layer or intermediary component that sits between the instruction stream and the processor core. This intermediary translates new instructions into old instruction equivalents before execution, acting as a mediator that enables compatibility without requiring changes to the processor's fundamental microarchitecture. The intermediary handles the complexity of instruction translation while the core processor remains unchanged.
2Adaptability or versatility
If new instructions are implemented by modifying microarchitecture, then instruction functionality is improved, but design and testing workload increases
Solution Approach 1:
The patent performs preliminary translation of new instructions into old instruction equivalents before execution. The translation layer pre-processes incoming instructions, converting them into a format the old processor can handle. This preliminary action eliminates the need for time-consuming microarchitecture modifications and extensive redesign testing, as the translation mechanism can be implemented and validated independently of the core processor design.
3Adaptability or versatility
If instruction translation is performed, then new instructions can be executed on old processors, but execution speed may decrease
Solution Approach 1:
The patent applies partial translation only when necessary - specifically when new instructions are detected. The translation layer monitors the instruction stream and selectively translates only those instructions that are incompatible with the old processor, while allowing native old instructions to execute directly without translation overhead. This partial action approach minimizes the impact on execution speed while still achieving the goal of new instruction executability.
Data Source
AI summary
A method for executing target instructions and being used in a processor includes the steps of: receiving an instruction; determining whether the received instruction is a target instruction according to an operation code of the received instruction; when the received instruction is not the target instruction, executing the received instruction in a first mode; and when the received instruction is the target instruction, simulating the execution of the target instruction according to basic decoding information of the target instruction in a second mode. The basic decoding information includes the operation code, and is stored in an internal register.