Processor Instruction Translation for Wide Data Atomicity
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Solution Overview
Problem
Current processor architectures are limited in handling wider data bit widths, particularly for complex floating-point and vector instructions, as they can only process data up to a fixed 128-bit width, which is insufficient for modern processing needs.
Innovation Solution
The method involves translating macro-instructions into multiple micro-instructions, with specific micro-instructions marked as atomic operations, allowing for flexible execution and integration of results to expand the bit width processing capability while maintaining atomicity and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the processor uses a fixed 128-bit data bus width, then the processor architecture remains simple and manageable, but it cannot process data wider than 128 bits which limits processing capability for modern applications
Solution Approach 1:
The patent segments a single wide-bit macro-instruction into multiple narrower-bit micro-instructions that can be executed sequentially by the existing 128-bit execution unit. For example, a 256-bit macro-instruction is divided into two 128-bit micro-instructions, allowing the processor to handle wider data without requiring a physically wider data bus or execution unit.
Solution Approach 2:
The patent introduces a macro-instruction buffer and translation mechanism as an intermediary between the macro-instruction input and the micro-instruction execution unit. This intermediary translates wide-bit macro-instructions into sequences of narrow-bit micro-instructions, enabling the execution unit to process data wider than its native width without direct hardware modification.
2Adaptability or versatility
If macro-instructions are divided into multiple micro-instructions for processing, then the processor can handle wider data bit widths, but maintaining atomicity and ensuring correct integration of results becomes complex
Solution Approach 1:
The patent performs preliminary actions by translating the macro-instruction into multiple micro-instructions beforehand, marking them with atomicity flags, and preparing the execution sequence in advance. This preliminary translation and marking ensures that when the micro-instructions are executed, they maintain atomicity and can be correctly integrated without complex runtime decision-making.
Solution Approach 2:
The patent implements feedback mechanisms through atomicity flags and result integration logic that monitor the execution of micro-instructions. The system tracks whether micro-instructions belong to the same macro-instruction group and ensures that results are correctly integrated only when all micro-instructions complete successfully, providing feedback control to maintain reliability.
3Productivity
If the first micro-instruction stores its result directly in the architecture register, then execution is simple, but it causes error states in the architecture register when atomicity cannot be maintained
Solution Approach 1:
The patent introduces a buffer register as an intermediary between the micro-instruction execution and the architecture register. The first micro-instruction stores its result in the buffer register instead of directly in the architecture register. This intermediary holding area allows the system to complete atomic operations before transferring results to the architecture register, preventing error states while maintaining execution efficiency.
Data Source
AI summary
An instruction execution device includes a processor. The processor includes an instruction translator, a reorder buffer, an architecture register, and an execution unit. The instruction translator receives a macro-instruction and translates the macro-instruction into a first micro-instruction, a second micro-instruction and a third micro-instruction. The instruction translator marks the first micro-instruction and the second micro-instruction with the same atomic operation flag. The execution unit executes the first micro-instruction to generate a first execution result and to store the first execution result in a temporary register. The execution unit executes the second micro-instruction to generate a second execution result and to store the second execution result in the architecture register. The execution unit executes the third micro-instruction to read the first execution result from the temporary register and to store the first execution result in the architecture register.