Out-of-Order Processor Instruction Prioritization

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Solution Overview

Problem

Superscalar processors face inefficiencies in optimizing processor performance due to the traditional method of prioritizing the oldest ready instructions, which does not adequately address the importance of executing certain types of instructions like control transfer, flag setting, and address generation instructions as soon as possible, even if they are younger, to free up resources and improve performance.

Innovation Solution

Implementing a method where instructions are classified into categories and stored in separate queues based on their type, allowing for prioritization of control transfer, flag setting, and address generation instructions over other types, even if they are younger, by using an instruction classifier and scheduler to select instructions for execution based on relative priority.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the oldest ready instructions are prioritized for issue, then the re-order buffer does not fill up and stall the dispatching of instructions, but this policy alone does not ensure optimum processor performance

Engineering Contradiction:
Improveinstruction dispatching stabilityVSAvoidprocessor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The reservation station is divided into multiple instruction queues (first queue, second queue, third queue) that segment instructions based on their type and priority. Control transfer instructions go to the first queue, flag setting instructions to the second queue, and other instructions to the third queue, allowing differentiated handling of different instruction types

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different instruction queues are assigned different priority levels locally. The first queue (control transfer instructions) has highest priority, the second queue (flag setting instructions) has medium priority, and the third queue (other instructions) has lowest priority, enabling optimal execution order for each instruction type

Inventive Principle:
Principle #3Local quality

2Productivity

If certain types of instructions (control transfer, flag setting, address generation) are prioritized over other types even if younger, then resources are freed up faster and processor performance improves, but the selection mechanism becomes more complex

Engineering Contradiction:
Improveprocessor performanceVSAvoidinstruction selection mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Instructions are segmented into different categories based on their type, with each category having a dedicated queue. This segmentation simplifies the selection process by allowing the scheduler to systematically check queues in priority order rather than evaluating all instructions individually

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system changes the priority parameter of instructions based on their type rather than their age. Control transfer instructions are assigned high priority, flag setting instructions medium priority, and other instructions low priority, enabling performance optimization through parameter-based differentiation

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10001997B2Prioritizing instructions based on type
Publication Date: 2018.06.19 MIPS TECH INC
  • US10001997B2 patent drawing
  • US10001997B2 patent drawing
  • US10001997B2 patent drawing

AI summary

Methods and reservation stations for selecting instructions to issue to a functional unit of an out-of-order processor. The method includes classifying each instruction into one of a number of categories based on the type of instruction. Once classified an instruction is stored in an instruction queue corresponding to the category in which it was classified. Instructions are then selected from one or more of the instruction queues to issue to the functional unit based on a relative priority of the plurality of types of instructions. This allows certain types of instructions (e.g. control transfer instructions, flag setting instructions and/or address generation instructions) to be prioritized over other types of instructions even if they are younger.