Processor-Integrated Hash Circuit for Low-Latency Hashing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing software-implemented encryption methods for large data sets suffer from poor performance, particularly in the era of 'big data', and hardware solutions using adjunct circuits face bus and memory access latencies, limiting performance for small messages.
Innovation Solution
Implementing hash functions, such as SHA-3 and SHA-2, directly in a processor's execution unit with a hash circuit that includes a state register, state update circuit, and control circuit, enabling efficient processing through iterative rounds and hardware execution of hash instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If encryption is performed utilizing software executing on a general purpose processor, then the advantages of being able to select differing encryption algorithms and easily adapting a selected encryption algorithm to use various data lengths are achieved, but relatively poor performance is obtained
Solution Approach 1:
The encryption function is segmented into a dedicated execution unit within the processor, separate from the general-purpose processor core. This execution unit contains specialized circuitry for performing encryption operations, allowing the system to maintain software-level algorithm selection flexibility while achieving hardware-level performance through physical separation of encryption functions from general processing.
2Productivity
If support for encryption is provided in hardware to achieve improved performance, then encryption performance is improved, but the concern with encryption performance also arises due to the increased need to run enterprise applications utilizing encrypted data
Solution Approach 1:
The execution unit providing hardware encryption support is merged within the processor core rather than being implemented as a separate adjunct circuit. This integration allows the encryption functionality to share the processor's internal bus and memory structures, reducing overall system complexity while maintaining hardware-level encryption performance.
3Productivity
If hash functions are implemented separately from a processor core, for example, in a bus-attached Application-Specific Integrated Circuits (ASICs) or accelerator, then the possibility of better performance than some software solutions is offered, but bus and memory access latencies and messaging overhead limit performance
Solution Approach 1:
The hash function execution unit is merged within the processor core, sharing internal buses and memory structures with the main processor. This integration eliminates the need for separate bus transactions and messaging overhead that would occur with external ASIC or accelerator implementations, reducing access latency while maintaining hardware-level performance.
4Adaptability or versatility
If broad support in hardware for hash functions is provided, then hash function capability is enhanced, but large areas within a processor floorplan are consumed by circuitry implementing hash functions
Solution Approach 1:
The execution unit is designed to dynamically support multiple hash function algorithms through configurable circuitry rather than hardcoding support for each algorithm. This dynamic approach allows the same physical circuitry to adapt to different hash functions (SHA-1, SHA-2 family, SHA-3 family) based on the incoming instruction, providing broad algorithm support without requiring separate dedicated circuits for each algorithm.
Solution Approach 2:
The execution unit implements a universal hash function architecture that can perform multiple hash algorithms through a single configurable circuit. The circuit responds to different instruction types to execute SHA-1, SHA-2 variants, and SHA-3 variants, making one piece of circuitry serve multiple algorithmic functions and reducing the total area required compared to having separate dedicated circuits for each algorithm.
Data Source
AI summary
A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.