Processor Interconnect Link Counters for Utilization Monitoring
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Solution Overview
Problem
In parallel computers, communication delays due to concentrated link usage can significantly decrease application execution performance, and existing methods require modifying application programs to address this issue.
Innovation Solution
An information processing apparatus with multiple processors and links in various directions, featuring a network switch that includes link counters to track packet counts and a recorder to store these counts in memory without processor circuit control, allowing for visualization of link utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If link counters and recording mechanisms are added to monitor packet counts, then link utilization information becomes available for analysis, but device complexity increases
Solution Approach 1:
The link counters automatically count packets without requiring processor intervention, and the recorder autonomously transfers count values to memory when processors are idle. This self-service mechanism provides monitoring information while minimizing impact on processor operations and maintaining relatively simple device architecture.
Solution Approach 2:
The recorder acts as an intermediary component between the link counters and the processor memory system. It buffers count values and transfers them to memory during processor idle periods, thereby providing a simple mechanism to capture link utilization information without adding complex real-time processing requirements.
2Reliability
If link utilization monitoring is implemented, then communication bottlenecks can be identified, but processor throughput may be affected by additional control operations
Solution Approach 1:
The recorder transfers count values to memory periodically when processors are in idle states, rather than continuously interrupting processor operations. This periodic action during idle periods enables monitoring of communication performance while maintaining processor throughput, as the data transfer occurs only when processors are not actively executing application code.
Solution Approach 2:
The monitoring system operates autonomously during processor idle periods without requiring active processor control or intervention. The recorder independently manages the transfer of count values to memory, ensuring that processor throughput is not degraded by monitoring operations while still providing reliable communication performance data.
3Speed
If count values are stored in memory without processor control, then packet transmission timing is not affected, but device complexity increases
Solution Approach 1:
The recorder autonomously transfers count values to memory without requiring processor control or intervention. This self-service operation ensures that packet transmission timing is not affected by processor busy-waiting or interrupt handling, while the recorder mechanism itself remains relatively simple by leveraging existing memory interfaces and operating during processor idle periods.
Data Source
AI summary
An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.