Multi-Core Processor Inter-Core Interrupt Synchronization
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Solution Overview
Problem
Conventional multi-core processor architectures experience significant overhead during inter-process communications using FIFO buffers, requiring a large number of instructions for operation and synchronization, which limits processing capability and efficiency.
Innovation Solution
A processor architecture with inter-core interrupt signals and FIFO counters is implemented, allowing for efficient inter-process communications by synchronizing processes between processor cores using inter-core interrupt signals, FIFO counters, and an inter-core interrupt count setting register, reducing the overhead of instruction execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FIFO buffer approach is used for inter-process communications, then communication functionality is provided, but processing capability is not fully performed due to large overhead (200-300 clock cycles)
Solution Approach 1:
The patent segments the FIFO buffer access control into separate read-side and write-side control mechanisms. Each processor core has dedicated control logic for its respective side, allowing independent operation and reducing synchronization overhead. The read-side control includes read pointer management and read permission flags, while write-side control includes write pointer management and write permission flags, enabling parallel processing without global synchronization.
Solution Approach 2:
The patent implements dynamic access control where processor cores can switch between direct access mode and FIFO buffer access mode based on operational needs. The control logic dynamically adjusts access permissions and buffer pointers according to real-time conditions, allowing flexible and efficient inter-process communication without fixed overhead.
2Productivity
If multiple processor cores are integrated to improve computing performance, then parallel processing capability is increased, but power consumption and heat generation increase
Solution Approach 1:
The patent enables dynamic workload distribution across multiple processor cores through efficient inter-process communication. Processor cores can dynamically select whether to execute tasks locally or communicate through the FIFO buffer, optimizing energy consumption based on task characteristics and core availability. This dynamic scheduling reduces overall power consumption while maintaining high computing performance.
Data Source
AI summary
In one embodiment of the present invention, processor 1000 comprising a plurality of processor cores for processing an instruction-execution sequence is provided. Signal path 140 that is able to communicate an inter-core interrupt signal fint is connected to at least two processor cores 100A and 100B. Each core of the at least two cores has an inter-core interrupt count setting register (ICSR) 110 and a FIFO counter 120. Inter-core interrupt synchronization function, inter-core interrupt generation function, and FIFO counter updating function are implemented to the every core. In embodiments of the present invention, a core and a method therefor are also provided.