Processor Interrupt Handling via Parallel Mode Prediction

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Solution Overview

Problem

In processors with multiple processing elements, the overhead of backing up temporal data during periodic interrupts in multimedia applications is substantial, leading to increased memory requirements and processing time due to the need for parallel processing.

Innovation Solution

A processor with a first controlling unit that estimates the time required for parallel processing and a second controlling unit that predicts periodic interrupts, delaying the entry into parallel processing mode until the interrupt occurs, thereby reducing the need for data backup and optimizing task assignment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If parallel processing mode is entered to process tasks in parallel using multiple processing elements, then processing speed is improved, but overhead for backing up temporal data increases

Engineering Contradiction:
Improveprocessing speedVSAvoidoverhead time
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The controlling unit estimates the time required for parallel processing before entering the parallel processing mode, and predicts whether a periodic interrupt will occur during this period. This preliminary assessment allows the system to proactively avoid entering parallel processing mode when interrupts are expected, thereby preventing the overhead of data backup and restoration operations.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If parallel processing mode is used to process multimedia data, then productivity is improved, but memory requirements increase due to data backup

Engineering Contradiction:
ImproveproductivityVSAvoidmemory requirement
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

By estimating the parallel processing duration and predicting periodic interrupt occurrence in advance, the system avoids entering parallel processing mode when interrupts are anticipated. This prevents the need to allocate substantial memory for backing up temporal data of multiple processing elements, thereby reducing memory requirements while maintaining productivity.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If parallel processing mode is entered frequently, then processing efficiency is improved, but interrupt handling overhead increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidinterrupt handling time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system uses feedback from the prediction of periodic interrupts to control the entry into parallel processing mode. By continuously monitoring the timing of periodic interrupts and adjusting the decision to enter parallel processing mode accordingly, the system minimizes interrupt handling overhead while maintaining high processing efficiency.

Inventive Principle:
Principle #23Feedback

4Speed

If the processor enters parallel processing mode without prediction, then responsiveness is improved, but reliability decreases due to interrupt interruptions

Engineering Contradiction:
ImproveresponsivenessVSAvoidprocessing reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The controlling unit performs preliminary estimation of parallel processing time and prediction of periodic interrupt occurrence before entering the parallel processing mode. This advance preparation ensures that the processor maintains responsiveness by entering parallel mode when appropriate, while simultaneously improving reliability by avoiding entry when interrupts are expected, thus preventing processing interruptions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7877535B2Processor and interrupt handling method
Publication Date: 2011.01.25 SAMSUNG ELECTRONICS CO LTD
  • US7877535B2 patent drawing
  • US7877535B2 patent drawing
  • US7877535B2 patent drawing

AI summary

Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs.