Processor Interrupt Interface with Partition-Based Priority Blocking

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Solution Overview

Problem

Existing data processing systems face performance issues and increased complexity in managing interrupts in multi-processor environments due to the need for separate interrupt interfaces and software-based priority management, which leads to delays and overhead in handling partitioned or virtualized machines.

Innovation Solution

Implementing a processor-based interrupt management system that uses special purpose registers to evaluate partition ownership and priority directly, allowing interrupts to be delivered over a shared interface with context information, enabling independent priority management and reducing the need for hypervisor intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If separate interrupt interfaces are used for each processor core, then interrupt delivery latency is reduced, but device complexity and software overhead increase

Engineering Contradiction:
Improveinterrupt delivery latencyVSAvoidinterrupt controller design complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges multiple processor-specific interrupt interfaces into a single shared interrupt interface that serves all processor cores. The interrupt controller receives interrupt requests over this shared interface and uses partition identifiers and priority values to route interrupts to the appropriate target processors, eliminating the need for separate dedicated interfaces while maintaining efficient interrupt delivery

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interrupt controller is designed with universal functionality to handle interrupts for multiple processor cores through a single interface. It implements partition-based routing and priority-based arbitration mechanisms that enable one interface to perform the functions previously requiring multiple dedicated interfaces, reducing overall system complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If software-based priority management is used, then adaptability to different partition configurations is improved, but interrupt processing overhead and loss of time increase

Engineering Contradiction:
Improvepartition configuration adaptabilityVSAvoidinterrupt processing overhead
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The interrupt controller implements self-service functionality by automatically evaluating partition identifiers and priority values associated with each interrupt request. The controller independently determines routing decisions and priority arbitration without requiring software intervention, thereby reducing interrupt processing overhead while maintaining adaptability to different partition configurations through programmable routing tables

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary configuration of partition identifiers, priority values, and routing tables before interrupt processing occurs. This pre-configuration enables the interrupt controller to make rapid routing decisions based on pre-established rules, eliminating the need for software-based priority management during actual interrupt handling and reducing processing overhead

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If hypervisor intervention is required for interrupt routing, then partition management control is improved, but interrupt handling latency and productivity decrease

Engineering Contradiction:
Improvepartition management controlVSAvoidinterrupt handling efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent extracts the interrupt routing decision-making function from the hypervisor and relocates it to the interrupt controller hardware. The controller uses partition identifiers included with interrupt requests to autonomously determine routing decisions, eliminating the need for hypervisor intervention in the interrupt path and significantly improving interrupt handling efficiency while maintaining partition management control

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9436626B2Processor interrupt interface with interrupt partitioning and virtualization enhancements
Publication Date: 2016.09.06 EIREOG INNOVATIONS LTD
  • US9436626B2 patent drawing
  • US9436626B2 patent drawing
  • US9436626B2 patent drawing

AI summary

A method and circuit for a data processing system (200) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (35-38) located at the processor core (26) to enable quick and efficient interrupt priority blocking on a partition basis.