Processor Interrupt Pause Mechanism for Shared Memory Integrity
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Solution Overview
Problem
Current computer systems face challenges in preventing data corruption during interrupt contexts and shared memory access, where interrupts can occur mid-operation, leading to incorrect data access and corruption.
Innovation Solution
A processor architecture that includes a decoder, interrupt controller, and counter register, allowing for the specification of a count during which interrupts are paused or shared memory access is blocked, ensuring that operations are completed before resuming interrupt servicing or memory access, using machine code instructions like ATOMIC.END, ATOMIC.MEM, and ATOMIC.REG to manage these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupts are enabled during critical operations, then system responsiveness is improved, but data corruption risk increases
Solution Approach 1:
The patent applies preliminary action by setting up a counter mechanism before critical operations begin. The counter is initialized to a predetermined value that represents the number of instructions to be executed, and interrupt masking is enabled in advance. As instructions are decoded and executed, the counter is automatically decremented. This preliminary setup ensures that interrupt servicing is automatically restored after the critical section without requiring additional interrupt disable/enable operations, thus maintaining system responsiveness while protecting data integrity.
2Reliability
If interrupts are disabled during critical operations, then data corruption is prevented, but system responsiveness deteriorates
Solution Approach 1:
The patent implements dynamics by making the interrupt masking state dynamic rather than static. Instead of disabling interrupts for the entire duration of a function or operation, the system dynamically adjusts the interrupt masking duration based on the actual number of instructions being executed. The counter register holds a dynamic value that is decremented with each instruction, automatically determining when interrupt servicing should be restored. This dynamic approach minimizes interrupt latency while ensuring data integrity.
3Ease of operation
If traditional interrupt enabling/disabling methods are used, then interrupt servicing is simple, but resource usage increases
Solution Approach 1:
The patent applies self-service by implementing an automatic counter decrement mechanism that requires no additional processor intervention. The counter is automatically decremented with each instruction decoded and executed during the critical section. The interrupt masking is automatically restored when the counter reaches zero, eliminating the need for explicit interrupt enable instructions. This self-service approach reduces processor resource usage and energy consumption while maintaining simple interrupt servicing through the use of a dedicated counter register and automatic decrement logic.
Data Source
AI summary
Various embodiments include processors, methods, and computer program products providing pauses for interrupts and shared memory accesses. A processor may decode a machine code instruction, that machine code instruction including a quantity representing a count. As a result of decoding the instruction, the processor may set the value of the count in a status register. While the count is non-zero, the processor may pause servicing interrupts and/or may block another processor from performing operations on a shared memory resource. The processor may decrement the count with each subsequent decoded instruction. Servicing interrupts may be un-paused and/or access to the shared memory resource may be un-blocked once the count reaches zero.