Processor Interrupt Priority Control with Dynamic DISICTL Levels

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Solution Overview

Problem

Existing systems for managing interrupt priority levels in computer processors have limitations, such as the inability to effectively disable interrupts for devices with less deterministic execution times and limited compatibility with reentrant code.

Innovation Solution

The introduction of Disable Interrupt Control (DISICTL) instructions allows for the establishment and updating of a current DISICTL Interrupt Priority Level (IPL), which disables exceptions with an IPL equal to or below the current DISICTL IPL, enabling execution of high-priority code without interruptions from lower-priority exceptions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the DISI instruction is used to disable interrupts for a fixed period of time, then important code can execute without interruption, but the system loses flexibility for devices with less deterministic execution times

Engineering Contradiction:

Improvecode execution reliabilityVSAvoidadaptability to different execution time constraints

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent introduces a dynamic interrupt disable mechanism where the disable level can be adjusted based on the specific code execution requirements. Instead of a fixed-time disable, the system can dynamically set the interrupt disable level to match the actual execution time needs, providing flexibility for devices with non-deterministic execution times while ensuring reliable execution during critical periods.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of interrupt disable from a fixed time duration to a configurable interrupt level. This allows the system to adapt the interrupt disable behavior to different execution time constraints by adjusting the disable level parameter, thereby resolving the contradiction between reliability and adaptability.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the DISI instruction disables interrupts up to IPL6, then lower-priority interrupts are blocked, but higher-priority interrupts like IPL7 are still allowed which may be unwanted

Engineering Contradiction:

Improvecode execution reliabilityVSAvoidcontrol precision over interrupt disabling

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The patent applies local quality by allowing different interrupt levels to be disabled at different granularities. The DISICTL instruction enables selective disabling of specific interrupt levels (IPL0-IPL6) while maintaining the ability to allow higher-priority interrupts (IPL7) if needed. This provides precise control over which interrupt levels are blocked, resolving the contradiction between ensuring reliable execution and maintaining operational flexibility.

Inventive Principle:

Principle #3Local quality

3Reliability

If the DISI instruction is used, then interrupts are disabled for important code execution, but compatibility with reentrant code is limited

Engineering Contradiction:

Improvecode execution reliabilityVSAvoidcompatibility with reentrant code

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the interrupt disabling functionality into a separate controllable mechanism (DISICTL) that can be independently managed. This segmentation allows reentrant code to selectively enable/disable interrupt blocking at different levels, improving compatibility with reentrant code while maintaining the ability to ensure reliable execution of critical code sections.

Inventive Principle:

Principle #1Segmentation

4Ease of manufacture

If a fixed time disable mechanism is used, then implementation is simple, but it cannot accommodate devices with less deterministic execution times

Engineering Contradiction:

Improveimplementation simplicityVSAvoidadaptability to non-deterministic execution

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent changes the implementation from a fixed time parameter to a configurable interrupt level parameter. This parameter change maintains implementation simplicity while dramatically improving adaptability to non-deterministic execution times, as the interrupt disable level can be adjusted to match the actual execution time requirements of different devices and code sections.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12346722B2Systems and methods for managing interrupt priority levels

Publication Date: 2025.07.01 MICROCHIP TECHNOLOGY INC

AI summary

A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.