Processor System Interrupt Routing for Secure Maintenance
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Solution Overview
Problem
Current computing and communication systems face challenges in securely handling large software program codes and data for disparate applications, requiring efficient and secure processing of real-time and non-real-time tasks while being energy and power efficient, especially in mobile and e-commerce environments.
Innovation Solution
The development of electronic interrupt circuits and systems with multiple processor cores and modes, including secure and context-related modes, that utilize conversion circuits and power management systems to selectively route interrupts and adjust power settings, ensuring secure and efficient execution of applications and maintenance functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple processor cores with secure and context-related modes are implemented, then security and processing capability are improved, but device complexity increases
Solution Approach 1:
The processor system is divided into multiple independent processor cores, each capable of operating in different security modes (secure mode and non-secure mode). This segmentation allows each core to handle specific tasks with appropriate security levels, improving overall system security while distributing complexity across multiple units rather than concentrating it in a single complex processor
Solution Approach 2:
The patent introduces a new dimension of operation by implementing multiple security modes (secure and non-secure) that processor cores can switch between. This dimensional approach to security allows the system to handle different types of workloads with appropriate security protections without requiring completely separate hardware for each security level, thereby managing complexity more effectively
2Productivity
If conversion circuits are used to selectively route interrupts, then interrupt handling efficiency is improved, but device complexity increases
Solution Approach 1:
Conversion circuits are introduced as intermediary components between interrupt sources and processor cores. These circuits selectively route and convert interrupt signals based on the current security mode and context, ensuring that interrupts are handled efficiently and securely without requiring complex software intervention for each interrupt routing decision
Solution Approach 2:
The conversion circuits perform preliminary routing and filtering of interrupt signals before they reach the processor cores. By pre-processing interrupt signals and determining their appropriate destinations based on security modes and context, the system reduces the processing burden on the cores and improves overall interrupt handling efficiency while keeping the added complexity localized to the conversion circuit layer
3Use of energy by moving object
If power management systems adjust power settings dynamically, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The power management system dynamically adjusts power settings based on the operational state of processor cores, including their security modes and activity levels. This dynamic power management allows the system to optimize energy consumption by providing power to only the necessary components at the required levels, rather than maintaining constant high-power states for all components
Solution Approach 2:
The power management system incorporates feedback mechanisms that monitor the operational state of processor cores and adjust power delivery accordingly. By continuously monitoring system state and responding with appropriate power management decisions, the system achieves improved energy efficiency while keeping the control logic distributed and manageable rather than centralized and overly complex
Data Source
AI summary
A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.