Processor Interrupt Synchronization Loop with Dynamic Timeout
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Solution Overview
Problem
In information handling systems, processors with large cache sizes can be delayed in entering system management mode, leading to timeouts and potential system hangs when all processors are required to synchronize simultaneously, especially during events like demand-based switching.
Innovation Solution
A method is introduced where processors enter an entry synchronization loop, check if all processors have entered their interrupt handlers, calculate elapsed time, and determine the type of interrupt command to decide whether to exit the loop, allowing for increased timeout values for specific SMI types to ensure all processors synchronize correctly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processors with large cache sizes execute WBINVD instructions during SMI, then cache flushing is completed, but processor entry into SMI handler is delayed beyond 256 micro seconds causing timeout
Solution Approach 1:
The patent applies dynamics by making the timeout value adjustable rather than fixed. The system dynamically selects between a first timeout value (256 microseconds) for normal SMI handlers and a second, longer timeout value for SMI handlers requiring cache flushing. This dynamic adjustment allows the system to adapt to different processor states and instruction types, preventing premature timeouts while maintaining efficient processing for normal cases.
Solution Approach 2:
The patent changes the parameter of timeout value based on the specific SMI handler type and processor state. By detecting whether a processor is executing WBINVD or similar cache flushing instructions, the system modifies the timeout parameter accordingly. This parameter change resolves the contradiction by extending the timeout for cases where cache flushing is necessary, while maintaining the shorter timeout for standard operations.
2Reliability
If all processors must enter SMI handler simultaneously for synchronization, then system management mode is ensured, but processors executing cache flushing instructions may cause system hang
Solution Approach 1:
The system dynamically adapts the synchronization mechanism based on processor state. By detecting whether processors are executing cache flushing instructions, the system dynamically adjusts the timeout value to accommodate these delays. This prevents the harmful effect of system hangs while maintaining reliable synchronization for processors that do not require extended timeouts.
Solution Approach 2:
The patent implements feedback by having processors check the current timeout value and adjust their entry synchronization behavior accordingly. The system monitors processor state and provides feedback through the timeout mechanism, allowing processors to synchronize reliably without causing system hangs when cache flushing is involved.
3Productivity
If fixed timeout value of 256 microseconds is used for all SMI handlers, then normal SMI processing is efficient, but processors executing cache flushing instructions time out prematurely
Solution Approach 1:
The patent applies parameter changes by modifying the timeout value based on the specific requirements of different SMI handlers. Instead of using a fixed timeout, the system selects between a first timeout value (256 microseconds) for standard handlers and a second, extended timeout value for handlers that require cache flushing. This resolves the contradiction by maintaining efficiency for normal processing while ensuring reliability for cache flushing operations.
Solution Approach 2:
The patent applies local quality by treating different SMI handler types differently based on their specific requirements. Rather than applying a uniform timeout to all handlers, the system identifies local characteristics (whether cache flushing is needed) and applies appropriate timeout values accordingly. This allows optimal processing efficiency for standard handlers while ensuring reliable synchronization for handlers requiring extended timeouts.
Data Source
AI summary
A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, determine whether to exit the entry synchronization loop after the timeout value has been reached.