Processor Invalidate Page Instruction TLB Optimization
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Solution Overview
Problem
Conventional processors require complex and resource-intensive microcode routines to invalidate translation lookaside buffer (TLB) and paging cache entries, which can slow down processor performance.
Innovation Solution
A single invalidate page instruction is introduced, allowing the processor to perform a pseudo translation process that identifies and invalidates matching entries in the TLB and paging cache without accessing system memory, leveraging existing translation and caching structures to streamline the invalidation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional microcode routines are used to invalidate TLB and paging cache entries, then all matching entries can be invalidated, but the processor consumes valuable time and resources due to the complex manual search process
Solution Approach 1:
The TLB and paging cache structures perform self-validation by automatically detecting and invalidating their own matching entries when an invalidation request is received, eliminating the need for external microcode routines to manually search and invalidate each entry sequentially
Solution Approach 2:
The patent replaces the mechanical sequential search process implemented in microcode with a hardware-based parallel validation mechanism that uses the existing translation and caching structures to simultaneously identify and invalidate all matching entries across the TLB and paging cache
2Reliability
If conventional microcode routines manually search each TLB and paging cache entry, then matching entries can be invalidated, but the device complexity increases due to the complex invalidation process
Solution Approach 1:
The validation logic is embedded within the TLB and paging cache structures themselves, allowing them to autonomously identify and invalidate their own matching entries without requiring complex external control logic or microcode routines
Solution Approach 2:
The existing TLB and paging cache structures are made multi-functional by enabling them to perform both their primary translation/caching function and their own validation and invalidation function, eliminating the need for separate complex invalidation mechanisms
3Productivity
If a single invalidate page instruction is implemented, then processor time is reduced, but the device complexity increases due to the need for integrated validation capability
Solution Approach 1:
The TLB and paging cache structures are designed to perform multiple functions including address translation, caching, and self-validation, allowing a single invalidate page instruction to leverage these existing structures for rapid invalidation without requiring separate dedicated validation hardware
Solution Approach 2:
The existing TLB and paging cache structures serve as intermediaries between the invalidate page instruction and the actual invalidation action, enabling rapid invalidation by using the established translation and caching mechanisms to identify and invalidate matching entries
Data Source
AI summary
A processor including a translation lookaside buffer (TLB), an instruction translator, and a memory subsystem. The TLB caches virtual to physical address translations. The instruction translator incorporates a microinstruction set for the processor that includes a single invalidate page instruction. The invalidate page instruction, when executed by the processor, causes the processor to perform a pseudo translation process in which a virtual address is submitted to the TLB to identify matching entries in the TLB that match the virtual address. The memory subsystem invalidates the matching entries in the TLB. The TLB may include a data TLB and an instruction TLB. The memory subsystem may include a tablewalk engine that performs a pseudo tablewalk to invalidate entries in the TLB and in one or more paging caches. The invalidate page instruction may specify invalidation of only those entries indicated as local.