Processor and I/O Hub Integration on Single Die

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Solution Overview

Problem

Current processor and I/O hub implementations suffer from speed reduction, increased power consumption, and additional complexity due to the need for separate integrated circuit devices and additional circuitry, which also occupy more board space.

Innovation Solution

Integrating the I/O hub on the same IC device as the processor, utilizing a wider and slower bus, FIFO devices for deterministic data transfer, sideband signals for power management, and a protocol for controlling power states, while removing unnecessary logic for off-chip communication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the processor and I/O hub are provided on different IC devices, then communication between them can be implemented, but speed is reduced due to delay associated with communicating signals between the IC devices

Engineering Contradiction:
Improvecommunication speedVSAvoidseparate IC devices
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent integrates the I/O hub onto the same IC device as the processor, eliminating the need for separate IC devices and inter-device communication interfaces. This merging of previously separate components directly reduces signal transmission delay and improves communication speed between the processor and I/O hub.

Inventive Principle:
Principle #5Merging (Combining)

2Use of energy by moving object

If the processor and I/O hub are provided on different IC devices, then communication can be implemented, but power consumption increases due to presence of additional circuitry required to allow for communication between the IC devices

Engineering Contradiction:
Improvepower consumptionVSAvoidadditional circuitry
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

By integrating the I/O hub and processor on the same IC device, the patent eliminates additional communication circuitry such as inter-IC interfaces and associated control logic. This reduction in circuitry directly decreases power consumption while maintaining communication functionality.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If discrete I/O hub components are used, then communication functionality is provided, but additional board space is required

Engineering Contradiction:
Improveboard spaceVSAvoiddiscrete components
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent consolidates the I/O hub and processor into a single IC device, eliminating the need for separate discrete I/O hub components on the circuit board. This integration directly reduces the board space required while maintaining all necessary communication functionalities.

Inventive Principle:
Principle #5Merging (Combining)

4Loss of time

If a bus is used to communicate between separate IC devices, then communication can be established, but delay is introduced due to signal transmission between devices

Engineering Contradiction:
Improvecommunication delayVSAvoidbus interface
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

By integrating the I/O hub and processor on the same IC device, the patent eliminates the need for external bus interfaces and inter-IC communication pathways. This removal of the bus interface directly reduces signal transmission delay and improves communication responsiveness.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP2577477B1Integration of processor and input/output hub
Publication Date: 2018.01.10 INTEL CORP
  • EP2577477B1 patent drawingFigure 1
  • EP2577477B1 patent drawingFigure 2~3
  • EP2577477B1 patent drawingFigure 4

AI summary

Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.