Processor Key Generation Circuit for Decryption Latency
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Solution Overview
Problem
Software-implemented encryption in data processing systems experiences poor performance when handling large data sets, leading to slow decryption processes due to the need to regenerate encryption keys during the decryption process.
Innovation Solution
A processor design that includes an instruction fetch unit, an architected register file, and an execution unit with a key generation circuit, which generates and stores decryption keys during the encryption process, making them available at low latency for the decryption process, thereby accelerating decryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If encryption is performed in software on a general purpose processor, then encryption functions can be easily adapted and selected, but decryption performance deteriorates due to the need to re-generate keys during decryption
Solution Approach 1:
The patent applies preliminary action by generating and storing the decryption key during the encryption process itself. The key generation circuit generates a decryption key from the encryption key and stores it in an architected register before decryption is needed. This eliminates the need to re-generate keys during decryption, directly resolving the performance bottleneck while maintaining software adaptability through the instruction-based interface.
2Productivity
If encryption is performed in hardware to improve performance, then decryption speed improves, but device complexity increases due to additional key generation circuitry
Solution Approach 1:
The key generation circuit is designed to be multi-functional, handling both encryption key processing and decryption key generation within the same hardware structure. The circuit receives encryption keys, generates corresponding decryption keys through cryptographic functions, and stores them in existing architected registers. This universal approach provides hardware acceleration without requiring entirely separate decryption hardware, thus improving decryption speed while limiting complexity growth.
Solution Approach 2:
The encryption process serves itself by generating the decryption key during encryption. The same key generation circuit that processes encryption keys automatically produces and stores the corresponding decryption keys in architected registers. This self-service mechanism eliminates the need for separate key management hardware, achieving hardware-accelerated decryption performance without proportionally increasing device complexity.
3Reliability
If decryption keys are regenerated during decryption process, then security is maintained through key derivation, but time consumption increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-generating and storing decryption keys during the encryption process. The key generation circuit derives decryption keys from encryption keys using cryptographic functions and stores them in architected registers before decryption begins. This preliminary key preparation maintains security through proper key derivation while eliminating time-consuming key regeneration during decryption, directly addressing the time loss problem.
Data Source
AI summary
A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a key-generating instruction. The execution unit includes a key generation circuit that, responsive to a key-generating instruction, iteratively applies a cryptographic function to a sequence of iteration inputs beginning with an encryption key obtained from the architected register file and stores, within the architected register file, a decryption key obtained from at least one iteration of the cryptographic function.