Processor L1 Memory Segmentation for VLIW and Array Mode Performance
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Solution Overview
Problem
Conventional processors supporting both coarse-grained array and VLIW modes face performance deterioration due to high cache miss rates and inefficient data memory access patterns, especially when executing general routines and loop operations, as they rely solely on scratch pad memory for both modes, leading to poor execution performance and increased external memory bandwidth usage.
Innovation Solution
The processor is configured with a cache memory that caches variables for the VLIW mode and a scratch pad memory for the coarse-grained array mode, with separate memory sections (shared and local/stack) and an address decoding unit to determine the correct memory access, allowing the core to access either the cache or scratch pad memory based on the execution mode, and a data memory controller to manage external memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If only scratch pad memory is used for both coarse-grained array mode and VLIW mode, then device complexity is reduced, but performance deteriorates due to high cache miss rates and inefficient data memory access patterns
Solution Approach 1:
The patent divides the L1 memory into two separate sections: a scratch pad memory section for coarse-grained array mode and a cache memory section for VLIW mode. This segmentation allows each memory type to be optimized for its specific access patterns, with the scratch pad memory handling sequential access for loop operations and the cache memory handling random access for general routines, thereby improving overall execution performance without excessive complexity
Solution Approach 2:
The patent applies local quality by providing different memory characteristics to different access patterns: the scratch pad memory section provides high bandwidth for sequential access in coarse-grained array mode, while the cache memory section provides high capacity and locality for random access in VLIW mode. This localized optimization of memory properties for specific access patterns resolves the contradiction between simplicity and performance
2Device complexity
If scratch pad memory is accessed through data memory controller for both modes, then device complexity is reduced, but external memory bandwidth increases and performance deteriorates
Solution Approach 1:
The patent segments the memory access paths by providing a dedicated cache memory section that can be accessed independently from the scratch pad memory section. This allows the cache memory to serve VLIW mode operations without routing through the data memory controller, reducing external memory bandwidth usage and improving performance for general routines
Solution Approach 2:
The cache memory acts as an intermediary between the processor core and external memory for VLIW mode operations. By introducing this intermediate memory layer, the patent reduces the frequency of external memory accesses, thereby decreasing bandwidth consumption and improving overall performance without significantly increasing device complexity
Data Source
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AI summary
A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component.