Processor Large-Operand Multiplication Hardware Multiplier
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Solution Overview
Problem
As electronic commerce and communication increase, securing transactions and communications against tampering and unauthorized use becomes a significant challenge, with less sophisticated cryptographic algorithms becoming vulnerable due to advancements in computer technology, particularly as key sizes increase, leading to a dramatic rise in computational workload.
Innovation Solution
A processor is designed with an instruction set architecture that includes a hardware multiplier datapath circuit capable of multiplying large operands, allowing for single-instruction execution of large-operand multiplication instructions, thereby reducing the need for multiple programmer-selected instructions and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If key sizes are increased to bolster cryptographic security, then resistance to brute-force attacks is improved, but computational workload increases dramatically
Solution Approach 1:
The patent segments large-operand multiplication into multiple smaller multiplication operations that can be executed by standard hardware multipliers. The large operands are divided into smaller chunks, each processed by the hardware multiplier datapath circuit, with results combined to produce the final product. This segmentation allows cryptographic operations with large key sizes to be performed efficiently without requiring a complete redesign of the hardware multiplier.
Solution Approach 2:
The patent introduces an instruction execution unit as an intermediary between the software instruction and the hardware multiplier datapath circuit. This execution unit manages the complex sequence of operations required for large-operand multiplication, breaking down the task into manageable steps and coordinating the use of the hardware multiplier resource. The intermediary handles operand splitting, partial product accumulation, and result combination, freeing the hardware multiplier to focus on its core function.
2Adaptability or versatility
If multiple programmer-selected instructions are used to perform large-operand multiplication, then hardware limitations are worked around, but execution time and complexity increase
Solution Approach 1:
The patent merges multiple separate instructions into a single unified large-operand multiplication instruction. Instead of requiring programmers to sequence multiple instructions for splitting operands, performing multiple smaller multiplications, and combining results, the patent provides a single instruction that encapsulates the entire operation. The instruction execution unit interprets this single instruction and automatically performs all necessary sub-operations, significantly reducing execution time and simplifying the instruction stream.
Solution Approach 2:
The patent enhances the instruction execution unit with multi-functionality to handle both standard arithmetic operations and large-operand multiplication. The execution unit is designed to recognize and process the specialized large-operand multiplication instruction, automatically switching to the appropriate processing mode. This universal approach allows the same hardware to efficiently handle both conventional and large-operand multiplication without requiring separate dedicated circuits for each operation type.
Data Source
AI summary
A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M. In response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within the ISA other than the large-operand multiplication instruction.