Processor Leakage Current Variability Power Management
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Solution Overview
Problem
Modern processors face increased power consumption due to leakage current variability, which exceeds computation power and is exacerbated by smaller gate dimensions, leading to inefficiencies and uncertainty in power management.
Innovation Solution
A method involving the generation of a micro-architectural leakage map using computation data from power controllers and processor instruction counters, allowing for sub-unit power gating to manage leakage current variability, thereby optimizing power consumption and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fabrication processes use smaller gate dimensions to increase transistor density, then computation capacity is improved, but leakage current increases dramatically
Solution Approach 1:
The processor core is divided into multiple sub-units (e.g., execution units, functional units) that can be independently controlled. The power management apparatus segments the core into activable and inactivable sub-units, allowing selective deactivation of specific segments to reduce leakage current while maintaining computation capacity through remaining active segments.
Solution Approach 2:
Different sub-units of the processor core are assigned different operational states (active or inactive) based on their individual leakage characteristics and computational requirements. The power management apparatus applies local quality control by determining which specific sub-units should be active or inactive to optimize the balance between computation capacity and power consumption.
2Quantity of substance
If fabrication processes use smaller gate dimensions, then transistor density is improved, but leakage current variability increases
Solution Approach 1:
The power management apparatus incorporates feedback mechanisms that monitor the operational state and power consumption of processor sub-units. Based on this feedback, the system dynamically adjusts which sub-units are active or inactive, adapting to variations in leakage current caused by fabrication process variability. This feedback loop enables the system to maintain reliable operation despite increased leakage variability in scaled transistors.
3Productivity
If all sub-units remain active, then computation capacity is maintained, but power consumption increases due to leakage current
Solution Approach 1:
The power management apparatus implements dynamic control of sub-unit activation states. Instead of a static configuration where all sub-units remain active, the system dynamically adjusts which sub-units are active or inactive based on real-time computational requirements and power consumption conditions. This dynamic approach allows the system to maintain computation capacity when needed while reducing power consumption during low-utilization periods.
4Loss of energy
If sub-units are deactivated to reduce power consumption, then leakage current is reduced, but computation capacity may be compromised
Solution Approach 1:
The power management apparatus applies partial action by deactivating only specific sub-units that contribute significantly to leakage current, rather than deactivating the entire core. This selective approach allows the system to achieve meaningful leakage current reduction while maintaining sufficient computation capacity through the remaining active sub-units. The granularity of sub-unit control enables partial deactivation that optimizes the trade-off between power consumption and computation capacity.
Data Source
AI summary
Technologies are generally described to provide a leakage current variability based power management of a processor. According to some examples, instruction counters and aggregated power consumption of the processor may be used to process power measurements of the processor into linear equations. The linear equations may be processed to produce a set of leakage values for the processor. In an example scenario, computation data from a power controller and processor instruction counters (PICs) of a core of the processor may be used to determine the leakage current variability of the core. A table of linear combination samples may be generated from the computation data. A micro-architectural leakage map of the core may be generated from the linear combination samples within the table.