Processor Link Training Downgrade for Boot Reliability

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Solution Overview

Problem

Conventional information handling systems lack a means to recover from boot operation failures due to processor link training issues, particularly when processor links do not configure correctly, leading to higher boot failures, especially with repurposed PCIe links and loose or damaged cable connections.

Innovation Solution

An Information Handling System (IHS) that includes a bootloader engine to train processor links during boot operations according to a first link configuration, downgrades the configuration if initial training fails, and continues the boot process if retraining is successful, allowing the system to operate with downgraded links.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If processor links are trained according to a predefined link configuration during boot operations, then the system achieves proper link initialization and configuration, but the system becomes vulnerable to boot failures when links do not configure correctly due to loose or damaged cable connections

Engineering Contradiction:

Improveboot operation reliabilityVSAvoidlink training complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system performs preliminary link training during boot operations to initialize processor interconnect links before the operating system loads. This preliminary action ensures that links are properly configured early in the boot process, allowing the system to detect and recover from connection issues before full operation begins.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts link training parameters by attempting multiple link configurations with different speeds and widths. When a link fails to train at a higher configuration, the system automatically downgrades to a lower configuration, changing the operational parameters to achieve successful link initialization.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If the system provides multiple link configurations for processor interconnects, then the system adapts to different hardware configurations and cable conditions, but the boot operation becomes more complex and time-consuming

Engineering Contradiction:

Improvelink configuration adaptabilityVSAvoidboot operation time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs link training during the preliminary boot phase before the operating system loads, so that multiple configuration attempts are made early when time is available. This ensures adaptability to different hardware configurations while minimizing the impact on overall system startup time.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms during link training by monitoring whether each link configuration attempt succeeds or fails. Based on this feedback, the system automatically adjusts the training process, attempting higher configurations first and then downgrading only when necessary, thereby optimizing both adaptability and boot time.

Inventive Principle:

Principle #23Feedback

3Productivity

If processor links are configured at high speeds and widths, then the system achieves optimal performance, but the system becomes more sensitive to cable connection quality and more prone to boot failures

Engineering Contradiction:

Improvedata transmission speedVSAvoidboot operation reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The system prepares for potential link training failures by implementing a tiered configuration approach during boot operations. By attempting high configurations first and having predefined lower configurations ready as fallback options, the system cushions against the harmful effects of loose or damaged cable connections before they can cause boot failures.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10860512B2Processor interconnect link training system

Publication Date: 2020.12.08 DELL PROD LP

AI summary

A processing system interconnect link training system includes a processing system that includes a secondary processing subsystem that is coupled to a first primary processing subsystem and a second primary processing system which are coupled to each other via a processing system interconnect that includes a plurality of processing system links. The secondary processing subsystem trains, during a boot operation and according to a first link configuration, the plurality of processing system links. Then the secondary processing subsystem determines that the training of the plurality of processing system links fails and, in response, retrains the plurality of processing system links according to a second link configuration that is a downgraded configuration relative to the first link configuration. The second processing subsystem then determines that the retraining of the plurality of processing system links according to the second link configuration was successful and, in response, continues with the boot operation.