Processor Load Assignment for Parallel Processing Bottlenecks

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Solution Overview

Problem

Conventional parallel processing techniques in computer systems suffer from performance degradation due to uneven processing amounts among multiple processes, leading to bottlenecks and poor load balance, which can significantly reduce the efficiency of applications like those calculating force between particles.

Innovation Solution

An information processing apparatus that measures the maximum operating frequency of each processor and the load value of each process, then assigns processes to processors based on their performance variations and load values to optimize processing distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If processes are assigned to processors without considering performance variations, then device complexity is reduced, but parallel processing performance deteriorates due to bottlenecks and poor load balance

Engineering Contradiction:
Improveparallel processing performanceVSAvoidprocessor assignment complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs preliminary measurement of maximum operating frequencies for all processors before actual parallel processing begins. These measurements are stored and used to inform subsequent process assignments, ensuring that high-performance processors are identified and utilized appropriately for load-balanced parallel execution

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the assignment parameter from simple round-robin or static allocation to dynamic assignment based on measured operating frequency parameters. By using frequency measurements as the basis for assignment decisions, the system optimizes parallel processing performance while managing complexity through parameter-driven automation

Inventive Principle:
Principle #35Parameter changes

2Productivity

If processes are assigned uniformly to processors, then ease of operation is improved, but productivity decreases due to bottlenecks caused by uneven processing amounts

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidassignment management simplicity
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The system applies different assignment strategies to different processors based on their individual performance characteristics. High-frequency processors receive higher-load processes while lower-frequency processors handle lighter loads, creating locally optimized assignments that improve overall productivity without requiring complex manual intervention

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system uses measured frequency data as feedback to automatically adjust process assignments. This feedback mechanism enables the system to adapt to actual processor capabilities, improving processing efficiency while maintaining operational simplicity through automated decision-making based on empirical measurements

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11397659B2Information processing apparatus, information processing method, and storage medium
Publication Date: 2022.07.26 FUJITSU LTD
  • US11397659B2 patent drawing
  • US11397659B2 patent drawing
  • US11397659B2 patent drawing

AI summary

An information processing apparatus, includes a memory; and a first processor coupled to the memory and configured to: identify a maximum operating frequency of each of a plurality of second processors, when executing a plurality of processes to be subjected to parallel processing by the plurality of second processors, measure a load value representing a magnitude of a load of each of the plurality of processes, and determine, based on the identified maximum operating frequency of each of the plurality of second processors and the measured load value of each of the plurality of processes, a specific processor as an assignment destination of each of the plurality of processes from the plurality of second processors.