Processor Load Balancing via Diverse-Redundant Instruction Block Assignment

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Solution Overview

Problem

Existing methods for executing diverse-redundant instruction sequences fail to effectively distribute and execute instructions between processors, leading to potential incorrect results and difficulty in error detection due to lack of redundancy in processing.

Innovation Solution

The method involves dividing instruction sequences into blocks and assigning them to processors based on execution time indicators, with alternating and nested assignment strategies to ensure redundant execution, allowing for cyclic execution and error verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If diverse-redundant instruction sequences are executed by multiple processors, then reliability is improved through error detection capability, but execution time increases due to redundant processing

Engineering Contradiction:

Improveerror detection capabilityVSAvoidexecution time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The instruction sequences are divided into instruction blocks that can be distributed across multiple processors. This segmentation allows redundant execution to proceed in parallel rather than sequentially, maintaining reliability benefits while reducing the time penalty through concurrent processing of different instruction blocks by different processors

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instruction sequences are pre-processed to identify and separate instruction blocks before distribution. This preliminary analysis enables optimal assignment of instruction blocks to processors based on execution time indicators, ensuring that redundant execution can proceed efficiently with minimal overhead during actual execution

Inventive Principle:

Principle #10Preliminary action

2Productivity

If instruction sequences are distributed to multiple processors, then load balancing is improved, but execution time deviations between processors increase

Engineering Contradiction:

Improveload balancingVSAvoidexecution time deviation

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The system uses execution time indicators as parameters to guide the distribution of instruction blocks among processors. By calculating and comparing these indicators, the system dynamically adjusts which processors receive which instruction blocks, achieving load balancing while compensating for differences in processor speeds and characteristics to minimize execution time deviations

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The system calculates execution time indicators for different instruction blocks and uses this information to make informed distribution decisions. This feedback mechanism ensures that instruction blocks are assigned to processors in a way that balances the workload and minimizes timing deviations, with the execution time indicators serving as the feedback parameter for optimization

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11354132B2Load balancing of two processors when executing diverse-redundant instruction sequences

Publication Date: 2022.06.07 WAGO VERW GMBH

AI summary

A method and a system are presented for load balancing of two processors when executing diverse-redundant instruction sequences.