Processor Load Data Prediction via Training Tables
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Solution Overview
Problem
Conventional processors face challenges in reducing memory read latency, particularly due to high latency in Level-1 data cache access and dependencies in address calculation, which hinder computational speed.
Innovation Solution
The implementation of a training table and register table system that predicts load data by identifying frequently repeating loads, allowing subsequent instances to use predicted values stored in registers, thereby bypassing actual memory reads and reducing dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is read from Level-1 data cache, then data retrieval is performed, but latency of at least 5 cycles is incurred
Solution Approach 1:
The patent performs preliminary actions by predicting load data values before actual memory access occurs. The predictor circuit generates predicted values during earlier pipeline stages (decode or allocate), allowing subsequent execution stages to use these predictions immediately, thereby eliminating the 5+ cycle L1 cache latency for repeated loads.
Solution Approach 2:
The patent implements dynamic prediction by tracking the dynamic behavior of load instructions through training tables and register tables. The system adapts to patterns in load addresses and data values, dynamically adjusting predictions based on observed repetition patterns, thereby reducing latency for dynamically repeating loads.
2Measurement precision
If address calculation dependencies are resolved, then accurate address computation is achieved, but resolution can take 10 cycles or more
Solution Approach 1:
The patent performs preliminary address prediction by using training tables to store historical address information and generating predicted addresses before full dependency resolution. This allows the execution pipeline to proceed with predicted addresses while dependency resolution continues in parallel, reducing the 10+ cycle delay.
Solution Approach 2:
The patent introduces intermediary structures (training tables and register tables) that mediate between dependency resolution and execution. These tables store intermediate address and data value information, allowing the execution unit to operate with predicted values while the full dependency chain resolves in the background.
3Loss of time
If predicted load data is used in execute stage, then memory latency is reduced, but prediction accuracy must be maintained
Solution Approach 1:
The patent implements feedback mechanisms where the actual load data returned from memory is compared with predicted values. Mismatches trigger updates to the training tables and register tables, refining future predictions. This feedback loop maintains high prediction accuracy while enabling latency reduction through early prediction usage.
Solution Approach 2:
The patent uses dynamic adaptation where prediction accuracy is continuously adjusted based on observed patterns. The training tables dynamically learn from actual memory access patterns, and the register tables are updated to reflect current data values, ensuring predictions remain accurate even as program behavior changes.
Data Source
AI summary
Disclosed embodiments relate to predicting load data. In one example, a processor a pipeline having stages ordered as fetch, decode, allocate, write back, and commit, a training table to store an address, predicted data, a state, and a count of instances of unchanged return data, and tracking circuitry to determine, during one or more of the allocate and decode stages, whether a training table entry has a first state and matches a fetched first load instruction, and, if so, using the data predicted by the entry during the execute stage, the tracking circuitry further to update the training table during or after the write back stage to set the state of the first load instruction in the training table to the first state when the count reaches a first threshold.