Processor Load Step Balancing With Proportional Clock Control
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Solution Overview
Problem
Conventional load balancing techniques for processor clock frequency fail to maintain stable power supply voltage during sudden load changes, leading to either power supply voltage undershoot or overshoot, causing fault conditions.
Innovation Solution
Proportional reduction of processor clock frequency in response to load increases, ensuring minimal change in current draw from the power rail, thereby maintaining stable power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor clock frequency is lowered during periods of increased processing demand, then the power supply voltage stability is improved, but the processing throughput deteriorates
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by detecting changes in the number of active execution units and proportionally adjusting the clock frequency accordingly. The system transitions from static frequency settings to dynamic frequency modulation that adapts to real-time processing demands, resolving the contradiction between maintaining voltage stability and preserving processing throughput.
Solution Approach 2:
The patent changes the clock frequency parameter in direct proportion to the change in active execution units. When the number of active execution units increases by a factor of N, the clock frequency is reduced by the same factor N, maintaining a proportional relationship that balances power consumption with processing capacity and prevents voltage droop while optimizing throughput.
2Reliability
If the clock frequency is halved during increased load periods, then the power supply voltage droop is reduced, but the processing performance deteriorates significantly
Solution Approach 1:
Instead of applying a fixed 50% frequency reduction (excessive action), the patent applies a proportional frequency reduction that matches the actual increase in processing demand. The frequency is reduced by a factor equal to the increase in active execution units, which is often less than doubling, thus avoiding excessive frequency reduction and preserving more processing performance while still preventing voltage droop.
3Reliability
If the clock frequency is reduced proportionally to the increase in active execution units, then the current demand stability is improved, but the system complexity increases
Solution Approach 1:
The patent implements a feedback mechanism where the system continuously monitors the number of active execution units and adjusts the clock frequency in response to detected changes. This closed-loop feedback control stabilizes current demand by ensuring that frequency reduction matches load increase, preventing voltage droop while maintaining a relatively simple implementation through direct proportional adjustment.
Data Source
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AI summary
A system is provided that controls the clocking of a processor depending upon its usage of execution units. As the processor transitions from a default mode of operation using a default number of the execution units to an increased load mode of operation using an increased number of the execution units, a current drawn by the processor from a power rail remains substantially unchanged.