Processor Local Bus Bridge with Crossbar Switch for FPGA Frequency Adaptation
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Solution Overview
Problem
The performance of programmable logic devices (PLDs) like FPGAs is limited by the disparity between the operating parameters of embedded processors and the FPGA fabric, leading to bottlenecks in operations such as memory access, and the integration of ASIC cores reduces flexibility and manufacturing yield.
Innovation Solution
A processor local bus bridge with a crossbar switch and frequency adaptation mechanisms is introduced to bridge the gap between the processor block and the FPGA fabric, enabling bidirectional communication and address mapping to optimize data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If embedded processors are designed apart from PLDs with higher operating frequencies, then processing speed is improved, but performance is limited by disparity between operating parameters of embedded processor and FPGA fabric
Solution Approach 1:
The patent introduces a bridge circuit as an intermediary component between the embedded processor and FPGA fabric. This bridge includes frequency conversion logic that translates between the high-frequency processor clock domain and the lower-frequency FPGA clock domain, enabling efficient data transfer without direct coupling. The intermediary handles protocol conversion and timing synchronization, resolving the parameter disparity issue.
Solution Approach 2:
The patent implements dynamic frequency scaling and voltage adjustment mechanisms that allow the embedded processor to operate at optimal frequencies for different workloads. The system can dynamically change operating parameters such as clock frequency, voltage levels, and bus width to match the requirements of connected FPGA fabric, thereby improving overall system productivity while maintaining high processing speed capability.
2Productivity
If ASIC cores are integrated to enhance performance, then data throughput is improved, but design flexibility is reduced
Solution Approach 1:
The patent divides the system into distinct modular segments: embedded processor core, bridge circuit, and FPGA fabric. Each segment can be independently designed, configured, and optimized. The bridge circuit itself is segmented into separate functional blocks for frequency conversion, protocol handling, and data buffering, allowing selective optimization of specific functions without affecting the entire system architecture.
Solution Approach 2:
The patent implements dynamic reconfiguration capabilities where the bridge circuit can adapt its operating characteristics in real-time based on system requirements. The system can dynamically adjust frequency multiplication factors, buffer sizes, and protocol handling modes, providing flexibility comparable to fully programmable logic while achieving ASIC-level performance optimization for specific functions.
3Productivity
If frequency adaptation mechanisms are introduced to align operating frequencies, then data transfer rate is improved, but device complexity increases
Solution Approach 1:
The patent designs the bridge circuit with multi-functional blocks that can perform multiple operations. For example, the frequency conversion logic can simultaneously handle clock generation, phase alignment, and duty cycle adjustment. The data buffer can operate in multiple modes including FIFO, circular buffer, and direct throughput, depending on configuration. This universality reduces overall device complexity by consolidating functions into fewer, more versatile components.
Data Source
AI summary
A processor local bus bridge for a processor block ASIC core for embedding in an IC is described. A core logic-to-core logic bridge includes a slave processor local bus interface, a crossbar switch coupled to the slave processor local bus interface and a master processor local bus interface coupled to the crossbar switch. The slave processor local bus interface and the master processor local bus interface are coupled to one another via the crossbar switch for bidirectional communication between a first and a second portion of core logic. The bridge provides rate adaptation for bridging for use of a frequency of operation associated with the crossbar switch which has substantially greater frequencies of operation than those associated with the core logic sides of the master and slave processor local bus interfaces.