Processor Local Coherency for Virtualized I/O Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Scalability issues arise in fully coherent multiprocessor systems with increasing numbers of virtual I/O devices and processors, leading to increased complexity and resource consumption due to the need for each processor to track all I/O operations across the system.
Innovation Solution
Implementing processor local coherency by selectively routing physical addresses and associated data from virtual I/O devices directly to the originating processor instead of shared memory, allowing each processor to cache and store data independently, reducing the need for system-wide coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full coherency is implemented in a multiprocessor system with virtualized I/O devices, then data consistency across all processors is maintained, but system complexity and resource consumption increase significantly as the number of processors and virtual I/O devices increases
Solution Approach 1:
The patent segments the unified coherency domain into processor-specific coherency domains. Each processor maintains coherency only with its assigned virtual I/O devices rather than tracking all I/O operations across the entire system. This segmentation reduces the complexity of coherency management while maintaining data consistency within each processor's designated scope.
Solution Approach 2:
The patent implements local coherency where each processor has dedicated coherency management for its specific virtual I/O devices. Instead of requiring all processors to participate in system-wide coherency protocols, each processor independently manages coherency for locally assigned devices, reducing overall system complexity and resource consumption.
2Reliability
If each processor tracks all I/O operations across the system to maintain full coherency, then data consistency is ensured, but power consumption and processing overhead increase
Solution Approach 1:
By dividing the coherency management responsibility into processor-specific segments, each processor only monitors and manages I/O operations for its assigned virtual devices. This eliminates the need for processors to track all system-wide I/O operations, significantly reducing processing overhead and power consumption while maintaining coherency within each processor's domain.
Solution Approach 2:
The patent implements partial coherency action where processors perform coherency management only for their specific virtual I/O devices rather than all devices in the system. This partial action approach provides sufficient coherency for each processor's workloads without the excessive overhead of full system-wide coherency tracking.
3Reliability
If system-wide coherency protocols are used to manage virtualized I/O devices, then all processors can access consistent data, but bus congestion and shared resource consumption increase
Solution Approach 1:
The patent segments the I/O address space and coherency management into processor-specific portions. Each processor communicates with its assigned virtual I/O devices through dedicated or prioritized pathways, reducing contention on shared system buses. This segmentation allows parallel I/O operations from multiple processors without causing bus congestion, while maintaining data consistency within each processor's domain.
Solution Approach 2:
The system performs preliminary assignment of virtual I/O devices to specific processors, establishing dedicated coherency domains before I/O operations begin. This preliminary action prevents unnecessary bus traffic by ensuring that I/O operations are directed to the appropriate processor's domain, reducing shared resource contention and improving overall bus throughput.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output.