Processor Lock Instruction Atomic Grouping
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Solution Overview
Problem
The strict application of atomic and fencing properties in lock instructions leads to processor slowdowns due to the need for younger instructions to wait for older instructions to complete, especially in cases of uncontested locks that have to execute serially.
Innovation Solution
An atomic grouping unit identifies older store instructions that can be locked with the current lock instruction, creating an atomic group, allowing the lock to be completed speculatively without waiting for older stores to write to memory, and using probe processing logic to negatively acknowledge probes until all older stores in the atomic group have written to cache memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strict application of atomic and fencing properties is enforced, then correctness of lock instructions is ensured, but processor speed deteriorates due to serialization delays
Solution Approach 1:
The patent applies dynamics by making the lock completion process adaptive rather than static. The completion detector dynamically determines whether to complete the lock speculatively or wait for older stores based on runtime conditions. This allows the system to switch between conservative (correctness-focused) and aggressive (speed-focused) modes, resolving the contradiction between reliability and speed.
Solution Approach 2:
The patent changes the parameter of lock completion timing from fixed (must wait for older stores) to variable (can complete speculatively or wait). By introducing a completion detector that monitors conditions and adjusts completion behavior, the system can optimize the timing parameter based on whether older stores are present, thus improving speed without sacrificing correctness.
2Reliability
If lock instructions complete serially waiting for older stores, then atomic property is maintained, but productivity decreases due to unnecessary waiting
Solution Approach 1:
The patent applies preliminary action by having the completion detector proactively identify when older stores are absent and prepare for speculative completion in advance. Instead of waiting passively for older stores to complete, the system提前 detects the opportunity for speculative execution and initiates it, thus improving productivity while maintaining atomicity through subsequent validation.
Solution Approach 2:
The patent uses feedback mechanisms where the completion detector continuously monitors the state of older stores and adjusts lock completion behavior accordingly. When older stores are detected as complete, the system feedbacks this information to allow speculative completion; when older stores are pending, it feedbacks to enforce serial completion, thus maintaining atomic property while maximizing throughput.
3Speed
If speculative completion is allowed, then processor speed improves, but risk of incorrect execution order increases
Solution Approach 1:
The patent applies dynamics by making the completion detection and validation process adaptive. The system dynamically switches between speculative and conservative completion based on the presence of older stores. This dynamic approach allows speed improvement through speculation when safe, while maintaining reliability through validation when necessary.
Solution Approach 2:
The completion detector acts as an intermediary between the lock instruction and the execution pipeline. It mediates the completion process by detecting whether speculative completion is safe and coordinating the validation of execution order. This intermediary ensures that speculative execution does not compromise reliability while still enabling speed improvements.
Data Source
AI summary
A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.