Processor Frequency Control Using Lockstep Core Comparison

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Solution Overview

Problem

Existing methods for adjusting processor frequency are inefficient in ensuring consistent performance and error detection across multiple cores, leading to potential errors and performance inconsistencies.

Innovation Solution

Implementing a lockstep mode using a firmware engine to synchronize and compare output data across multiple processor cores, adjusting frequency based on error detection and output equivalence, and utilizing a lookup table to manage frequency settings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If frequency adjustment techniques are implemented to improve processor performance, then operational performance is improved, but consistency and error detection across multiple cores deteriorate

Engineering Contradiction:
Improveprocessor performanceVSAvoidconsistency across cores
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements lockstep mode where multiple cores execute identical instructions simultaneously, creating copies of the same computational task across different cores. This allows for direct comparison of outputs to detect errors while maintaining synchronized frequency adjustment across all participating cores, thus ensuring consistency while improving performance through parallel execution.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent incorporates output comparison mechanisms that provide feedback between cores operating in lockstep mode. When cores execute the same instructions, their outputs are compared to detect discrepancies indicating errors. This feedback loop enables error detection without compromising the frequency-adjusted performance of individual cores, as the comparison occurs transparently in the background.

Inventive Principle:
Principle #23Feedback

2Reliability

If lockstep mode is implemented with firmware engine to synchronize cores, then error detection is improved, but device complexity increases

Engineering Contradiction:
Improveerror detectionVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs a firmware engine that serves multiple functions: it manages frequency adjustment across cores, initiates lockstep mode, coordinates output comparison, and handles error detection. By consolidating these diverse functions into a single firmware component rather than requiring separate hardware circuits for each function, the implementation achieves robust error detection while minimizing the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If frequency is adjusted based on core allocation using lookup table, then productivity is improved, but manufacturing precision of performance characteristics worsens

Engineering Contradiction:
Improveoperational efficiencyVSAvoidperformance consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent utilizes a lookup table that stores pre-determined frequency values corresponding to different numbers of allocated cores. When cores are allocated to a workload, the system queries the lookup table to determine the appropriate frequency setting. This parameter change approach allows rapid frequency adjustment based on core allocation, improving productivity while maintaining consistent performance characteristics through pre-calibrated frequency values that account for variations in core configurations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260111320A1Frequency adjustment for processors
Publication Date: 2026.04.23 NVIDIA CORP
  • US20260111320A1 patent drawing
  • US20260111320A1 patent drawing
  • US20260111320A1 patent drawing

AI summary

Apparatuses, systems, and techniques adjust a frequency at which a processor operates. In at least one embodiment, a frequency at which a processor operates is adjusted based, at least in part, on different cores of the processor performing one or more identical instructions.