Processor Logic Simulation Acceleration System
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Solution Overview
Problem
Current vector-based verification methodologies for integrated circuits, such as simulation and emulation, are time-consuming and inefficient, especially as IC designs become more complex, due to limitations in leveraging multi-core processors and the need for design migration between simulation and emulation environments.
Innovation Solution
A unified emulation and simulation acceleration system that partitions IC design logic at abstraction levels like ESL, RTL, or GL, allowing concurrent execution on multiple processors with minimized data exchange and optimized load balancing, enabling faster runtime performance by managing tasks and communication effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-core general processors are used to accelerate simulation, then simulation speed should improve, but the speed up ratio is not high because the event-based simulation engine core is difficult to unleash the power of multi-core processors
Solution Approach 1:
The patent divides the IC design into multiple partitions at abstraction levels (ESL, RTL, GL) that can be executed as separate threads or processes on different CPU cores. This segmentation enables parallel execution of design portions, directly addressing the difficulty of utilizing multi-core processors by creating independent work units that can be distributed across cores.
Solution Approach 2:
The system dynamically manages task scheduling and load balancing across multiple processors based on the partitioned design. The emulator can adaptively assign partitions to available processors and adjust execution strategies during runtime, enabling flexible utilization of multi-core architecture to maximize simulation acceleration.
2Productivity
If FPGA based emulator is used, then runtime speed is fast and cost is low, but compile time is long due to time-consuming place and routing step
Solution Approach 1:
The patent performs preliminary partitioning of the design at abstraction levels before the actual emulation execution. By pre-partitioning the design into manageable units, the system avoids time-consuming place and routing steps during compile time, while still achieving fast runtime performance through the partitioned concurrent execution model.
3Loss of time
If traditional processors-based emulator is used, then compile time is fast and runtime speed is decent, but price tag is high and power consumption is high
Solution Approach 1:
The patent creates a virtualized emulation environment that copies the essential functionality of traditional expensive emulators onto standard multi-core processors. By implementing the emulation engine as software that partitions and executes design units concurrently on available CPU cores, the system achieves emulator-like performance without requiring expensive dedicated hardware, thereby reducing both cost and power consumption.
4Adaptability or versatility
If migration from simulation environment to emulation environment is performed, then verification capability is enhanced, but it takes time involving design coding change and testbench modification
Solution Approach 1:
The patent creates a unified verification platform that can operate in both simulation and emulation modes using the same partitioned execution framework. The system accepts design descriptions at multiple abstraction levels and can execute them either as traditional simulation or as concurrent emulated tasks, eliminating the need for separate migration processes and reducing verification setup time.
Data Source
AI summary
An emulation and simulation acceleration system includes a plurality of processors, wherein each of the plurality of processors is configured to run a separate simulation task in a parallel manner. Each of the plurality of processors includes a local memory for instructions and data, a memory space for saving received data from other processors of the plurality of processors. The system includes a plurality of connection channels between each processor of the plurality of processors, wherein each of the plurality of connection channels is either virtual or physical, and each of the plurality of connection channels extends through computer hardware or memory mapping. The system includes a plurality of system interfaces configured to interface with other systems for expansion to a larger system or to connect with external target system. Each of the plurality of system interfaces contains a virtual interface and a physical interface for connecting with other simulators.