Processor Architecture for Coarse-Granularity Matrix Operations
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Solution Overview
Problem
Conventional processors face inefficiencies when processing complex computing tasks in artificial intelligence due to fine-granularity instructions, requiring numerous instruction combinations and frequent data exchanges between the processor and memory, leading to low efficiency.
Innovation Solution
A processor architecture with an instruction fetching unit, decoder, and execution units that embed address information directly in instructions, allowing for coarse-granularity operations by determining execution units, source and destination addresses, and data amounts based on operation type and parameter fields, reducing the complexity of instruction decoding and enabling batch data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fine-granularity instructions are used for processing computing tasks, then the processor can execute basic operations with precision, but the computing task requires numerous instruction combinations leading to low efficiency
Solution Approach 1:
The patent merges multiple fine-granularity instructions into a single coarse-granularity instruction that can perform matrix operations directly. The instruction includes source address field, destination address field, operation type field, and operation parameter field, allowing the processor to execute entire matrix operations in one instruction rather than combining many basic operations, thus improving computing efficiency while maintaining operational precision
Solution Approach 2:
The patent changes the granularity parameter of instructions from fine to coarse. The instruction structure includes operation type field (indicating matrix multiplication, matrix addition, or activation function calculation) and operation parameter field (indicating matrix dimensions), enabling the processor to handle complex computing tasks with fewer, more efficient instructions
2Ease of operation
If conventional instructions are executed, then basic operations can be performed, but data needs to be frequently exchanged between the processor and memory resulting in very low efficiency
Solution Approach 1:
The patent implements an on-chip memory nested within the processor that can store matrix data directly. The instruction set includes instructions for writing matrix data to on-chip memory and performing matrix operations using data from on-chip memory, reducing the need for frequent data exchange with external memory and significantly improving processing efficiency
3Adaptability or versatility
If a complex computing task is divided into many instruction combinations, then the task can be processed step by step, but the complexity of instruction decoding increases
Solution Approach 1:
The patent extracts the operation details (matrix dimensions, operation type) directly into the instruction fields themselves. The operation parameter field contains information about matrix dimensions, and the operation type field specifies the operation to be performed, eliminating the need for complex decoding logic to determine these parameters and simplifying the instruction decoding process
Data Source
AI summary
A processor and a method for executing an instruction on a processor are provided. In the method, a to-be-executed instruction is fetched, the instruction including a source address field, a destination address field, an operation type field, and an operation parameter field; in at least one execution unit, an execution unit controlled by a to-be-generated control signal according to the operation type field is determined, a source address and a destination address of data operated by the execution unit are determined according to the source address field and the destination address field, and a data amount of the data operated by the execution unit controlled by the to-be-generated control signal is determined according to the operation parameter field; the control signal is generated; and the execution unit in the at least one execution unit is controlled by using the control signal.