Processor Memory Access Monitor for Overlap Detection
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Solution Overview
Problem
Current processor technologies face inefficiencies in data processing due to the bottleneck of memory access, where processors wait for data from memory, leading to increased execution time and reduced efficiency, especially in AI processors with multiple cores.
Innovation Solution
Implement a method where a computing device dynamically monitors address segments occupied by memory access instructions, suspends execution of overlapping instructions, and updates remaining address ranges to refine memory access control, reducing unnecessary waiting delays and improving processor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor executes memory access instructions in parallel to improve processing efficiency, then the productivity increases, but the waiting time increases due to memory access bottlenecks
Solution Approach 1:
The patent applies preliminary action by having the first memory access instruction complete its entire address range access before allowing the second memory access instruction to execute. The system monitors the address range of the first instruction and only permits the second instruction to proceed when the first has fully completed, preventing overlapping executions that would cause waiting delays.
Solution Approach 2:
The patent introduces an intermediary monitoring mechanism that tracks the execution status and address range of memory access instructions. This intermediary component detects when the first instruction has completed its address range and coordinates the execution timing of subsequent instructions, eliminating the need for processor waiting while maintaining proper access sequencing.
2Reliability
If the processor waits for memory data to reduce access conflicts, then the reliability of data access is improved, but the productivity decreases due to increased execution time
Solution Approach 1:
The patent applies dynamics by making the execution flow adaptive rather than static. Instead of always waiting for memory data, the system dynamically monitors address ranges and only enforces sequential execution when address overlap is detected. When no overlap exists, instructions execute in parallel, optimizing both reliability and productivity based on real-time conditions.
Solution Approach 2:
The patent implements feedback through continuous monitoring of memory access address ranges. The system receives feedback about the completion status and address boundaries of executing instructions, and uses this feedback to dynamically control whether subsequent instructions should wait or proceed, ensuring data access reliability without unnecessary productivity loss.
3Reliability
If the processor implements strict sequential memory access to avoid conflicts, then the reliability of memory access is improved, but the loss of time increases due to unnecessary waiting
Solution Approach 1:
The patent applies local quality by applying different execution rules to different instruction pairs based on their specific address ranges. Instead of universally enforcing sequential access, the system monitors each instruction's address range locally and only imposes waiting delays when actual address overlap is detected, maintaining reliability only where necessary and reducing unnecessary time loss.
Data Source
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AI summary
The disclosure discloses a method and an apparatus for executing instructions, a device and a computer readable storage medium in a field of chips and artificial intelligence, and relates to a field of chips and artificial intelligence. The detailed implementation includes: obtaining a first memory access instruction for execution, in which the first memory access instruction includes a first address range of a memory to be accessed; in response to detecting a predetermined instruction for monitoring an accessed address range of the memory, executing the predetermined instruction to obtain a remaining address range not accessed by the first memory access instruction in the first address range; comparing the remaining address range with a second address range included in a second memory access instruction to be executed; and suspending execution of the second memory access instruction in response to the remaining address range at least partially overlapping with the second address range. With the method of the disclosure, address segment occupied by memory access instructions may be dynamically monitor, waiting delays of processor may be reduced, and performance of the processor may be improved.