Multi-Processor Memory Access Protection Using Secure Bus Monitoring
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Solution Overview
Problem
IoT devices with multiple processors face increased vulnerability to malicious code injection due to complex processing requirements, necessitating sophisticated detection and protection of memory regions.
Innovation Solution
Implementing a secure processor operating in a secure execution environment, a centralized address protection table (CAPT), and a transaction monitoring system to block unauthorized access to memory regions, using a security bus module to manage transactions and monitor stack regions for multiple processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors are added to handle complex processing requirements, then processing capability is improved, but vulnerability to malicious code injection increases
Solution Approach 1:
The memory system is segmented into multiple protected memory regions, each with specific access permissions. The CAPT divides memory protection into granular regions that can be independently controlled, allowing the system to maintain multiple processors while limiting the potential impact of malicious code injection to specific memory segments rather than the entire system.
Solution Approach 2:
The CAPT acts as an intermediary layer between processors and memory regions. It mediates all access requests by validating whether the requesting processor has permission to access the target memory region, thereby preventing unauthorized access and malicious code injection without restricting the functional capabilities of multiple processors.
2Reliability
If access protection mechanisms are implemented for memory regions, then security is improved, but transaction processing complexity increases
Solution Approach 1:
The CAPT pre-configures access permissions for each memory region before transactions occur. By establishing the valid master and access permissions in advance, the system avoids complex runtime decision-making, as the CAPT simply needs to check against pre-defined rules rather than evaluating complex access policies during each transaction.
Solution Approach 2:
The CAPT performs automatic validation of access permissions without requiring external intervention for each transaction. The system self-manages the security checks by automatically comparing the requesting processor against the stored valid master information, reducing the burden on external security management mechanisms.
3Productivity
If DMA channels are configured for processor access, then data transfer efficiency is improved, but risk of unauthorized memory access increases
Solution Approach 1:
Each DMA channel is configured with specific source and destination address regions that define its local access permissions. This local quality approach allows different DMA channels to have different access rights tailored to their specific functions, enabling efficient data transfer while limiting each channel's access to only the memory regions it is authorized to reach.
Data Source
AI summary
An electronic device includes a plurality of processors including a secure processor operating in a secure execution environment and a processor group including at least one processor, one or more processors including processing circuitry, and a memory storing instructions and data related to the plurality of processors. The instructions, when executed by the one or more processors individually or collectively, cause the electronic device to block a transaction, issued by an unauthorized processor from among the plurality of processors, with respect to an access prevention memory region, based on access prevention memory region information including a valid master, identification information of the access prevention memory region, and properties of the access prevention memory region.