Processor Memory Access Unit with Programmable Property Detection
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Solution Overview
Problem
Existing processor designs face poor clock speed due to the need to dynamically program cache properties of physical memory addresses, which increases logical depth in memory access paths.
Innovation Solution
A processor design incorporating a memory access unit, a cache unit, and a programmable physical memory property detection unit, which determines cache properties in the current clock cycle and performs memory access operations based on these properties in the next clock cycle, reducing logical depth and improving clock speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dynamic cache property detection is implemented for each physical memory address, then cache performance can be optimized, but processor clock speed deteriorates due to increased logical depth in memory access paths
Solution Approach 1:
The patent performs cache property detection in advance during the current clock cycle before the memory access operation needs to execute in the next clock cycle. The detection unit determines cache properties (cacheable or non-cacheable) of physical memory addresses proactively, so that when the memory access instruction executes, the detection result is already ready to be used immediately, eliminating the need for detection during the critical memory access path and thus not increasing logical depth.
Solution Approach 2:
The patent divides the memory access process into distinct functional units: a memory access unit for generating addresses, a programmable physical memory property detection unit for determining cache properties, and a cache unit for executing memory access operations. This segmentation allows each unit to operate independently and in parallel, with the detection unit working in the current clock cycle while the cache unit prepares for the next clock cycle, thereby avoiding sequential dependency that would increase logical depth.
2Productivity
If cache property detection is performed in the current clock cycle, then memory access operations can be optimized in the next clock cycle, but device complexity increases due to additional detection units and control logic
Solution Approach 1:
The detection unit is designed with multi-functionality to determine various cache properties (cacheable, non-cacheable, and programmable cache properties) of different memory addresses using a unified detection mechanism. This universal approach allows the same detection unit to handle multiple cache property types without requiring separate dedicated detection circuits for each property type, thereby reducing overall device complexity while maintaining comprehensive cache optimization capabilities.
Solution Approach 2:
The patent implements dynamic cache property detection that adapts to different memory access scenarios. The detection unit can dynamically determine cache properties based on the current memory access instructions and address patterns, allowing the system to optimize cache behavior in real-time without requiring complex static configuration logic. This dynamic approach simplifies the control logic by using rule-based detection that responds automatically to varying memory access patterns.
Data Source
AI summary
The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.