Processor Memory Alias Bypass for Image Data Processing
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Solution Overview
Problem
Existing processor technologies face performance degradation when handling large amounts of image data due to memory dependency issues, particularly with unpredictable memory operations like pointer variables, leading to inefficient scheduling and potential incorrect results during image processing.
Innovation Solution
The method involves reading data from memory using a vector-gather method, confirming and masking items with the same memory address, generating a correction value, and storing results using a vector-scatter method, while bypassing memory address alias checking to adjust compiler scheduling, thereby optimizing parallel processing of data such as weighted histograms without a separate hardware accelerator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory address alias checking is performed to ensure data correctness, then reliability is improved, but processing speed deteriorates due to conservative compiler scheduling
Solution Approach 1:
The patent extracts the memory address alias checking operation from the normal compilation and execution flow, separating it into a distinct analysis phase. By pre-identifying and removing alias checking requirements before code generation, the compiler can produce aggressive optimized code without the overhead of runtime alias checks, thus resolving the contradiction between reliability and processing speed
Solution Approach 2:
The patent performs memory address alias analysis as a preliminary action before code generation and compilation. By analyzing and resolving potential alias conflicts in advance, the system eliminates the need for conservative scheduling during actual execution, allowing both reliable data handling and high processing speed to coexist
2Reliability
If conservative scheduling is used to handle memory dependency, then reliability is improved, but productivity deteriorates due to degraded compiler performance
Solution Approach 1:
The patent extracts memory dependency analysis from the main compilation loop, performing it as a separate preliminary pass. This allows the compiler to make informed scheduling decisions based on pre-analyzed dependency information rather than using conservative defaults, improving both reliability and productivity
Solution Approach 2:
By performing memory dependency analysis as a preliminary action before code generation, the system obtains accurate dependency information in advance. This enables the compiler to generate optimized code with aggressive scheduling without risking correctness, thus improving compiler performance while maintaining reliability
3Reliability
If pointer variable scheduling is performed with memory dependency consideration, then reliability is improved, but processing speed deteriorates due to unpredictable memory operations
Solution Approach 1:
The patent extracts pointer variable alias analysis from the general memory dependency checking, treating it as a special case that can be analyzed and resolved separately. By identifying pointer alias relationships in advance through static analysis, the system can schedule pointer operations aggressively without runtime checks, improving processing speed while maintaining reliability
Data Source
AI summary
Methods and apparatuses for parallel processing data are disclosed. One method includes reading items of data from a memory using at least memory access address, confirming items of data with the same memory address among the read items of data, and masking the confirmed items of data other than one of the confirmed items of data. A correction value is generated for the memory access address using the confirmed items of data, and an operation is performed on data that has not been masked using the confirmed items of data and the correction value. Data obtained by operating on the data that has not been masked is stored as at least on representative data item for the data items with the same memory address. A schedule of a compiler of a processor is adjusted by performing bypassing of memory access address alias checking for at least one memory access address.