Processor Memory Bank Power Management for IoT Cryptographic Operations
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Solution Overview
Problem
Low power processor systems, such as IoT devices, face inefficiencies in memory power management during sleep and active cycles, leading to unnecessary power consumption due to inadequate memory bank allocation and state transitions during cryptographic operations.
Innovation Solution
A method that allocates memory banks dynamically based on predetermined sizes required for cryptographic operations, switching between active, retention, and power-down states to minimize power usage, by precomputing required space and splitting heap regions according to SRAM bank sizes, and selectively activating only necessary banks during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory banks are kept in active state to ensure sufficient heap space for cryptographic operations, then the reliability of cryptographic operation execution is improved, but the power consumption increases significantly during inactive periods
Solution Approach 1:
The memory system is divided into multiple independent memory banks that can be individually controlled. The heap region is partitioned across these banks, allowing selective activation of only the necessary banks for cryptographic operations rather than keeping all banks active continuously. This segmentation enables fine-grained power management while ensuring sufficient memory capacity when needed.
Solution Approach 2:
The memory bank states are dynamically adjusted based on operational requirements. The system transitions memory banks between active, retention, and power-down states depending on whether cryptographic operations are currently executing or can be deferred. This dynamic state management allows the system to optimize the balance between available heap space and power consumption in real-time.
2Use of energy by moving object
If memory banks are switched to power-down state to reduce power consumption during inactive periods, then the power consumption is reduced, but the time required to become fully operational again increases
Solution Approach 1:
Different memory banks are assigned different quality levels of retention. Some banks maintain retention state (preserving data but consuming minimal power) while others enter full power-down state. This local differentiation allows the system to optimize between retention time and power savings based on the specific operational context and criticality of data in each bank.
Solution Approach 2:
The system performs preliminary allocation and pre-warming of memory banks during low-activity periods. By pre-activating or retaining specific banks that are likely to be needed soon, the system reduces the wake-up time when cryptographic operations are required, while still maintaining power savings during extended inactive periods.
3Adaptability or versatility
If the heap region is divided into multiple sections corresponding to different memory banks, then the adaptability of memory allocation to different cryptographic operations is improved, but the device complexity increases
Solution Approach 1:
The heap region is segmented into multiple sections, each mapped to specific memory banks. This segmentation allows the memory manager to independently control which sections are active based on the current cryptographic operation requirements. The segmentation is implemented through standard memory management data structures, maintaining adaptability while controlling complexity through conventional techniques.
Data Source
AI summary
The processor system includes a processor coupled to a memory having a plurality of memory banks and a region configurable as a heap region. At least one memory bank is allocated to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation. At least one further memory bank is allocated to the heap region. The processor system may switch between first and second operating states. The first operating state has a lower power consumption than the second operating state. The processor system switches between a first and second operating mode by setting at least one memory bank and at least one further memory bank to an active state. The processor system switches between the second and first operating mode by setting at least one memory bank to a retention state and the at least one further memory bank to a power-down state.