Processor Memory Manager Selective Instruction Fetching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In a processor with a staged execution pipeline, the fetching of instructions that are not executed can inefficiently consume bandwidth and resources, leading to latency issues due to access to slow memory and potential system bottlenecks.

Innovation Solution

The memory manager selectively retrieves instructions based on a determination of whether the processor will execute them, using a benign instruction or value, such as a NOP instruction, to avoid fetching unused instructions from memory, thereby preventing resource tying and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the processor fetches all instructions from memory in a staged execution pipeline, then the pipeline can operate continuously without stalls, but bandwidth and memory resources are wasted on instructions that will not be executed

Engineering Contradiction:
Improvepipeline operation continuityVSAvoidbandwidth and memory resource consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The system performs preliminary determination of whether an instruction will be executed before actually fetching it from memory. The controller predicts branch outcomes and uses this prediction to decide in advance whether to fetch the next instruction, preventing wasted memory accesses while maintaining pipeline flow

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system extracts only the necessary instructions from memory based on predicted execution paths. By taking out only instructions that are likely to be executed and leaving out those that won't be executed (such as instructions after predicted branch targets), the system reduces memory bandwidth consumption while maintaining pipeline operation

Inventive Principle:
Principle #2Taking out (Extraction)

2Quantity of substance

If the processor accesses slow memory to retrieve instructions, then all instructions can be fetched, but latency increases due to the slow access time

Engineering Contradiction:
Improvenumber of instructions fetchedVSAvoidmemory access latency
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The system performs partial fetching by retrieving only the subset of instructions that are predicted to be executed, rather than fetching all possible instructions. This partial action approach reduces the total number of memory accesses and consequently reduces the cumulative latency impact on the pipeline

Inventive Principle:
Principle #16Partial or excessive action

3Quantity of substance

If the processor retrieves unused instructions from memory, then the instruction queue remains full, but system resources are tied up and efficiency decreases

Engineering Contradiction:
Improveinstruction queue fill levelVSAvoidprocessor efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The system uses feedback from branch prediction outcomes and instruction execution patterns to dynamically control instruction fetching. When predictions indicate certain instructions will not be executed, the controller adjusts fetching behavior accordingly, optimizing the balance between queue utilization and resource efficiency

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system determines in advance which instructions should be fetched based on branch predictions and execution context analysis. This preliminary determination prevents the queue from being filled with useless instructions, maintaining efficient resource utilization while keeping the queue adequately populated

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9817665B2System and technique for retrieving an instruction from memory based on a determination of whether a processor will execute the instruction
Publication Date: 2017.11.14 SILICON LABORATORIES INC
  • US9817665B2 patent drawing
  • US9817665B2 patent drawing
  • US9817665B2 patent drawing

AI summary

A technique includes receiving a request from a processor to retrieve a first instruction from a memory for a staged execution pipeline. The technique includes selectively retrieving the first instruction from the memory in response to the request based on a determination of whether the processor will execute the first instruction.